Microprocessor performance mode control utilizing sensed temperature as an indication of microprocessor utilization

• US 7,464,277 B2
• Filed: 01/28/2005
• Issued: 12/09/2008
• Est. Priority Date: 01/28/2005
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Hijazi, Mohammed, Prosperi, Roberto
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Bae; Ji H
• Application Number:
  US11/046,433
• Publication Number:
  US 20060174146A1
• Time in Patent Office: 1,411 Days
• Field of Search: 713/320, 713/300, 713/322
• US Class Current: 713/320
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems are disclosed for controlling microprocessor (CPU) performance modes utilizing sensed temperatures as an indication of CPU utilization. By recognizing that temperature can be used as an indication of CPU utilization, higher performance modes can be entered as temperature increases, and lower performance modes can be entered as temperature decreases.

Claims

1. A method for controlling microprocessor performance modes, comprising:

providing at least two performance modes for a microprocessor with a first performance mode being higher than a second performance mode;

sensing an edge temperature related to an edge temperature of the microprocessor as an indication of microprocessor utilization;

sensing a core temperature related to a core temperature for the microprocessor as an indication of an over-heating condition;

selecting the first performance mode for the microprocessor if the sensed edge temperature rises above a first threshold level, the first threshold level being a non-danger threshold level;

selecting the second performance mode for the microprocessor if the sensed edge temperature falls below a second threshold level, the second threshold level being a non-danger threshold level; and

placing the microprocessor in a low power protection mode if the sensed core temperature rises above a danger threshold level, wherein the danger threshold level is different from the first and second threshold levels.

2. The method of claim 1, wherein the selecting steps are performed by control circuitry outside the microprocessor package.

3. The method of claim 2, wherein the placing step is performed by control circuitry within the microprocessor package.

4. The method of claim 1, further comprising initially setting the microprocessor in the second performance mode, invoking the first performance mode when the sensed edge temperature rises above the first threshold level, and returning to the second performance mode if the sensed edge temperature falls below the second threshold level.

5. The method of claim 1, wherein the first and second threshold levels are the same.

6. The method of claim 1, wherein the first and second threshold levels are different and the first threshold level is higher than the second threshold level.

7. The method of claim 6, wherein the microprocessor has only two performance modes.

8. The method of claim 1, wherein the microprocessor has three or more performance modes.

9. The method of claim 1, wherein the performance modes are controlled by adjusting a clock speed applied to the microprocessor, by adjusting a voltage supply applied to the microprocessor, or by adjusting both.

10. An information handling system having microprocessor performance mode control, comprising:

a microprocessor having at least two performance modes with a first performance mode being higher than a second performance mode;

an edge temperature sensor configured to sense edge temperatures related to the microprocessor as an indication of microprocessor utilization;

a core temperature sensor configured to measure core temperatures related to the microprocessor as an indication of an over-heating condition;

control circuitry coupled to receive a signal from the edge temperature sensor and to control the microprocessor performance mode, the control circuitry being configured to select the first performance mode for the microprocessor if the sensed edge temperature rises above a first threshold level and to select the second performance mode for the microprocessor if the sensed edge temperature falls below a second threshold level, the first and second threshold levels being non-danger threshold levels; and

protection control circuitry coupled to receive a signal from the core temperature sensor and to control the microprocessor to enter a low power protection mode if the core temperature exceeds a danger threshold level, wherein the danger threshold level is different from the first and second threshold levels.

11. The information handling system of claim 10, further comprising clock control circuitry coupled to the microprocessor to provide a clock speed input and voltage control circuitry coupled to the microprocessor to provide a voltage supply level input, the clock control circuitry and the voltage control circuitry being configured to receive control input signals from the control circuitry such that performance modes are controlled by adjusting a clock speed applied to the microprocessor, by adjusting a voltage supply applied to the microprocessor, or by adjusting both.

12. The information handling system of claim 10, where the microprocessor comprises performance mode control circuitry configured to set a performance mode based upon a control setting, the control setting being adjustable based upon an external control signal, and wherein the control circuitry is coupled to provide the control signal to the microprocessor.

13. The information handling system of claim 10, wherein the control circuitry is located external to a package for the microprocessor.

14. The information handling system of claim 10, wherein the control circuitry is configured to initially set the microprocessor in the second performance mode, to invoke the first performance mode when the sensed edge temperature rises above the first threshold level, and to return to the second performance mode if the sensed edge temperature falls below the second threshold level.

15. The information handling system of claim 13, wherein the protection control circuitry is located within a package for the microprocessor.

16. The information handling system of claim 15, wherein the control circuitry comprises a storage device configured to store BIOS software.

17. The information handling system of claim 10, wherein the microprocessor has only two performance modes.

18. The information handling system of claim 10, wherein the first and second threshold levels are the same.

19. The information handling system of claim 10, wherein the first and second threshold levels are different and the first threshold level is higher than the second threshold level.

20. The method of claim 10, wherein the microprocessor has three or more performance levels.