High performance serial bus testing methodology

• US 7,464,307 B2
• Filed: 03/25/2003
• Issued: 12/09/2008
• Est. Priority Date: 03/25/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Glass, Richard J., Schoenborn, Theodore Z., Martwick, Andrew W., Nejedlo, Jay J., Wiznerowicz, Mike, Ellis, David G.
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US10/396,071
• Publication Number:
  US 20040204912A1
• Time in Patent Office: 2,086 Days
• Field of Search: 714733-734, 714/30, 714/738, 714/712, 714/758, 370/248, 370/366, 710/311, 710/71
• US Class Current: 714/712
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica

Abstract

According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Claims

1. An apparatus comprising:

a PCI Express bus having two or more lanes;

a first transmitter component coupled to a first lane of the PCI Express bus;

a second transmitter component coupled to a second lane of the PCI Express bus, the first and second transmitter components each having;

a pattern generator to generate test patterns; and

a serializer to serialize data to be transmitted from the transmitter on to the PCI Express bus;

a first receiver component coupled to the first lane of the PCI Express bus having a first pattern checker to receive the test pattern from the first lane; and

a second receiver component coupled to the second lane of the PCI Express bus having a second pattern checker to receive the test pattern from the second lane.

2. The apparatus of claim 1, further comprising;

a first debug module to correct errors detected at the first pattern checker; and

a second debug module to correct errors detected at the second pattern checker.

3. The apparatus of claim 1, wherein the first and second receiver components further comprises a deserializer.

4. The apparatus of claim 1, wherein the first and second pattern generators stores a first pattern of bits.

5. The apparatus of claim 4, wherein the first and second pattern checkers stores a second pattern of bits.

6. The apparatus of claim 5, wherein the first and second pattern checkers compares a pattern received from the first and second lanes with the second pattern of bits stored in the first and second pattern checkers.

7. The apparatus of claim 6, wherein the first and second receiver components includes logic to determine if an error occurs while transferring a pattern from the first and second transmitter components to the first and second receiver components, the logic operating based on the comparison.

8. The apparatus of claim 7, wherein the apparatus includes a mechanism to load a user defined pattern of bits into the first and second pattern generators as the first pattern of bits and to load the user defined pattern of bits into the first and second pattern checkers as the second pattern of bits.

9. The apparatus of claim 6, wherein the first and second pattern checkers compares the received pattern wit the second pattern of bits stored in the first and second pattern generators based upon a direct compare method.

10. The apparatus of claim 6, wherein the first and second pattern checkers compares the received patterns with the second pattern of bits based upon a multiple input register (MISR) testing methodology.

11. The apparatus of claim 1, further comprising logic to switch between a normal mode and a test mode, the first and second pattern checkers, operating in the test mode to determine if an error occurs during transmission of bits across the PCI Express bus.

12. The apparatus of claim 1, further comprising:

a training buffer to train the first and second lanes by testing sequences that are to be received via the first and second receivers.

13. The apparatus of claim 1, wherein the first and second pattern checkers and the first and second pattern generators comprise on-die circuitry provided within silicon of the apparatus.

14. A computer system comprising:

a point-to-point serial interconnect coupled to a transmitter component and a receiver component; and

a chipset, coupled to the point-to-point serial interconnect, including;

a first transmitter component coupled to a PCI Express bus;

a second transmitter component coupled to a second lane of the PCI Express bus, the first and second transmitter each having;

a pattern generator to generate test patterns; and

a serializer to serialize data to be transmitted from the transmitter on to the PCI Express bus;

a first receiver component coupled to the first lane of the PCI Express bus having a first pattern. checker to receive the test pattern from the first lane; and

a second receiver component coupled to the second lane of the PCI Express bus having a second pattern checker to receive the test pattern from the second lane.

15. The computer system of claim 14, wherein the chipset further comprises:

a first debug module to correct errors detected at the first pattern checker; and

a second debug module to correct errors detected at the second pattern checker.

16. The computer system of claim 14, wherein the first and second receiver components further comprises a deserializer.

17. The computer system of claim 14, wherein the chipset includes a mechanism to load a user defined pattern of bits into the first and second pattern generators as the first pattern of bits and to load the user defined pattern of bits into the first and second pattern checkers as the second pattern of bits.

18. The computer system of claim 17, wherein the first and second pattern checkers compares a pattern received from the first and second lanes with the second pattern of bits stored in the first and second pattern checkers.

19. The computer system of claim 17, wherein the first and second pattern checker compares the received patterns with the second pattern of bits based upon a multiple input register (MISR) testing methodology.

20. The computer system of claim 14, wherein the interconnect comprises a PCI Express bus.