Method and system or generating a current source model of a gate

• US 7,464,349 B1
• Filed: 10/11/2005
• Issued: 12/09/2008
• Est. Priority Date: 10/11/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Keller, Igor, Verma, Manuj
• Primary Examiner(s): Dinh; Paul
• Application Number:
  US11/246,060
• Time in Patent Office: 1,155 Days
• Field of Search: 716 4- 6, 703/14, 703 18- 19
• US Class Current: 716/136
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Aspects for generating a current source model of a gate include extracting the current source model of the gate. The current source model of the gate is a function of time and output voltage of the gate. Further, the current source model of the gate is extracted based on data present in a timing library. The aspects further include storing the current source model of the gate. This is carried out by using the existing, specified timing library for current source models. In this manner, additional expenditure is not incurred for formulating another timing library.

Claims

1. A method for generating a current source model of a gate, the gate included with at least one driving point and at least one receiving point in a circuit, wherein a load is applied on the gate, the method comprising the steps of:

a. extracting a current source model of the gate, the current source model of the gate being a function of time and output voltage of the gate and based on data from a timing library, the current source model defining the output current when the output voltage deviation is within a threshold value by a linear relationship described by;

I_out=g(t)*(V_out−

V_dc)

 

where I_out is the output current of the gate, g(t) is an admittance of the load, V_out is the output voltage of the gate, and V_dc is the voltage in accordance with a d.c. transfer curve for the gate, and, the current source model defining the output current when the output voltage deviation exceeds the threshold value by a non-linear relationship described by;

I_out=g(t)*[e<sup>−

α

(Vout−

Vdc)</sup>−

1]/α

 

where α

defines the gate'"'"'s non-linearity established through a fitting process; and

b. storing the current source model of the gate.

2. The method of claim 1, wherein extracting the current source model of the gate comprises:

a. ascertaining a pin capacitance as the load for the gate, the pin capacitance being added to the load before computing an output response of the gate; and

b. ascertaining a time shift for the gate as a time delay for the gate, the time shift being applied to the computed output response of the gate.

3. The method of claim 1, wherein the time is a function of an input slew of the gate.

4. The method of claim 1, wherein the output voltage of the gate is a function of input slew of the gate.

5. The method of claim 4, wherein the input slew is computed by accepting values from the timing library.

6. The method of claim 1, wherein extracting a current source model further comprises determining whether the load is zero, wherein if the load is zero, then the output voltage of the gate comprises the voltage according to the d.c. transfer curve for the gate.

7. The method of claim 6, wherein if the output voltage of the gate lies on the d.c transfer curve, then the current drawn by the gate is zero.

8. The method of claim 1, wherein the step of defining the output current when the output voltage deviation exceeds the threshold value includes the step of calculating α

from the relationship;

[(D₁−

D₂)/(τ

₁−

τ

₂)]*ln[(V_H/V_L)*((1−

α

V_L)/(1−

α

V_H))−

ln[V*/1−

α

V*]

where D₁,D₂ are respective delays corresponding to smallest input slew for the largest loads, τ

₁,τ

₂ are output slews corresponding to the largest loads, V_H is a high slew measurement threshold, V_L is a low slew measurement threshold and V* is a reference voltage that defines delay at a particular time.

9. A system for generating a current source model of a gate, wherein a load is applied on the gate, the system comprising:

a. means for extracting a current source model of the gate, the current source model of the gate being a function of time and output voltage of the gate and based on data from a timing library, said means for extracting a current source model of the gate including;

(i) means for defining the output current when the output voltage deviation is within a threshold value by a linear relationship described by;

I_out=g(t)*(V_out−

V_dc)

 

where I_out is the output current of the gate, g(t) is an admittance of the load, V_out is the output voltage of the gate, and V_dc is the voltage in accordance with a d.c. transfer curve for the gate, and,

(ii) means for defining the output current when the output voltage deviation exceeds the threshold value by a non-linear relationship described by;

I_out=g(t)*[e<sup>−

α

(Vout−

Vdc)</sup>−

1]/α

where α

defines the gate'"'"'s non-linearity established through a fitting process; and

b. means for storing the current source model of the gate.

10. The system of claim 9, wherein the means for extracting a current source model of the gate further comprises:

a. means for ascertaining a pin capacitance as the load for the gate, the pin capacitance being added to the load before computing an output response of the gate; and

b. means for ascertaining a time shift for the gate as a time delay for the gate, the time shift being applied to the computed output response of the gate.

11. The system of claim 9, wherein the means for extracting a current source model of a gate comprises determining whether the load is zero, wherein when the load is zero, the output voltage of the gate is according to the d.c. transfer curve for the gate and the current drawn by the gate is zero.

12. A computer program product for use with a computer, the computer program product comprising a computer usable medium having a computer readable program code embodied therein for generating a current source model of a gate by:

a. extracting a current source model of the gate, the current source model of the gate being a function of time and output voltage of the gate and based on data from a timing library, the current source model defining the output current when the output voltage deviation is within a threshold value by a linear relationship described by;

I_out=g(t)*(V_out−

V_dc)

 

where I_out is the output current of the gates g(t) is an admittance of the load, V_out is the output voltage of the gate, and V_dc is the voltage in accordance with a d.c. transfer curve for the gate, and, the current source model defining the output current when the output voltage deviation exceeds the threshold value by a non-linear relationship described by;

I_out=g(t)*[e<sup>−

α

(Vout−

Vdc)</sup>−

1]/α

 

where α

defines the gate'"'"'s non-linearity established through a fitting process; and

b. storing the current source model of the gate.

13. The computer program product of claim 12, further comprising:

a. ascertaining a pin capacitance as the load for the gate, the pin capacitance being added to the load before computing an output response of the gate; and

b. ascertaining a time shift for the gate as a time delay for the gate, the time shift being applied to the computed output response of the gate.

14. The computer program product of claim 12, wherein extracting a current source model further comprises determining whether the load is zero, wherein when the load is zero, the output voltage of the gate is according to the d.c. transfer curve for the gate and the current drawn by the gate is zero.