Post passivation interconnection schemes on top of IC chip
First Claim
Patent Images
1. A chip comprising:
- a silicon substrate;
a first internal circuit in or on said silicon substrate;
an ESD circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first via over said silicon substrate and in said dielectric layer, wherein said first via is connected to said ESD circuit;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;
a second via in said passivation layer and directly over said first via, wherein said second via is connected to said first via;
a third via in said passivation layer, wherein said third via is connected to said first interconnecting structure; and
a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said third via and said first interconnecting structure.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
19 Claims
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1. A chip comprising:
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a silicon substrate; a first internal circuit in or on said silicon substrate; an ESD circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first via over said silicon substrate and in said dielectric layer, wherein said first via is connected to said ESD circuit; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride; a second via in said passivation layer and directly over said first via, wherein said second via is connected to said first via; a third via in said passivation layer, wherein said third via is connected to said first interconnecting structure; and a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said third via and said first interconnecting structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A chip comprising:
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a silicon substrate; a first internal circuit in or on said silicon substrate; an ESD circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first via over said silicon substrate and in said dielectric layer, wherein said first via is connected to said ESD circuit; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride; a polymer layer over said passivation layer; a second via in said passivation layer and directly over said first via, wherein said second via is connected to said first via; a third via in said passivation layer, wherein said third via is connected to said first interconnecting structure; and a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said third via and said first interconnecting structure. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification