System and method for balancing cells in a battery pack with selective bypass paths

• US 7,466,104 B2
• Filed: 10/13/2006
• Issued: 12/16/2008
• Est. Priority Date: 10/13/2006
• Status: Active Grant

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: Wang, Wei, Li, Guoxing, Xiao, Sean
• Primary Examiner(s): TSO, EDWARD H
• Application Number:
  US11/580,507
• Publication Number:
  US 20080088277A1
• Time in Patent Office: 795 Days
• Field of Search: 320/116, 320/118, 320/119
• US Class Current: 320/118
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits

Abstract

A system and method for cell balancing with smart low-voltage control circuit. The cell balancing system comprises a plurality of battery cells, an external bypass path for each cell, an internal bypass path for each cell, an input terminal receiving an enable signal for each cell, an input terminal receiving a selection signal, and a cell balancing unit for generating a configuration signal to conduct the external bypass path or internal bypass path. The enable signal is configured to enable a bypass current of each cell, and the selection signal is configured to select the external bypass path or internal bypass path. The cell balancing unit is employed to receive signals from input terminals, and generate a configuration signal to control the conductance of external bypass paths or internal bypass paths.

Claims

1. A cell balancing circuit comprising:

a first cell;

a first bypass path for said first cell;

a second bypass path for said first cell;

a first input for receiving a first signal for conducting a bypass current of said first cell;

a second input for receiving a second signal for selecting either said first bypass path or said second bypass path for said first cell; and

a first driving circuit for receiving said first signal and said second signal, and for providing a third signal configured to selectively conduct either said first bypass path or said second bypass path for said first cell.

2. The cell balancing circuit as claimed in claim 1, further comprising:

a second cell coupled in series with said first cell;

a third bypass path for said second cell;

a fourth bypass path for said second cell;

a third input for receiving a fourth signal for conducting bypass current of said second cell;

a fourth input for receiving a fifth signal for selecting either said third bypass path or said fourth bypass path for said second cell; and

a second driving circuit for receiving said fourth signal and said fifth signal, and for providing a sixth signal configured to selectively conduct either said third bypass path or said fourth bypass path for said second cell.

3. The cell balancing circuit as claimed in claim 1, wherein said first signal comprises a low voltage signal received from a processor, wherein said processor determines whether said first cell needs to conduct said bypass current.

4. The cell balancing circuit as claimed in claim 1, further comprising:

a first switch selectively switched on by said first signal; and

a first current source coupled to said first switch for selectively providing a first bias current to said first driving circuit,

wherein said first bias current is configured to conduct said bypass current for said first cell.

5. The cell balancing circuit as claimed in claim 1, wherein said second signal comprises a low voltage signal received from said processor, and wherein said processor determines whether to select said first bypass path or said second bypass path.

6. The cell balancing circuit as claimed in claim 4, further comprising:

a second switch selectively switched on by said second signal; and

a second current source coupled to said second switch for selectively providing a second bias current to said first driving circuit,

wherein said second bias current is configured to select either said first bypass path or said second bypass path for said first cell.

7. The cell balancing circuit as claimed in claim 2, further comprising:

a serial control bus coupled from said first driving circuit to said fourth input and for transmitting said fifth signal to said fourth input.

8. The cell balancing circuit as claimed in claim 7, wherein said serial control bus comprises a fifth bypass path configured to perform over-voltage protection.

9. A cell balancing circuit comprising:

a plurality of cells of a battery pack;

an internal bypass path for each cell of said plurality of cells;

an external bypass path for each cell of said plurality of cells;

an input for receiving an enable signal for each cell of said plurality of cells, wherein said enable signal is configured to enable a bypass current of each cell of said plurality of cells;

a current source for each cell of said plurality of cells configured to provide a variable bias current, wherein said bias current selects among a combination of said internal bypass path and said external bypass path for each cell of said plurality of cells; and

a driving circuit for receiving said enable signal and said bias current for each cell of said plurality of cells, and for providing a configuration signal for each cell of said plurality of cells configured to selectively conduct among said combination for each cell of said plurality of cells.

10. The cell balancing circuit as claimed in claim 9, wherein said enable signal comprises a low voltage signal received from a processor, wherein said processor determines whether each cell of said plurality of cells needs to conduct said bypass current.

11. The cell balancing circuit as claimed in claim 9, further comprising:

a switch selectively switched on by said enable signal, wherein said switch coupled to said current source for selectively providing said bias current to said driving circuit.

12. The cell balancing circuit as claimed in claim 9, wherein said combination is selected from the group consisting of said internal bypass path, said external bypass path, and paths including both internal bypass path and said external bypass path.

13. The cell balancing circuit as claimed in claim 10, wherein said internal bypass path from said combination is selected when said bias current reaches a first predetermined level.

14. The cell balancing circuit as claimed in claim 13, wherein said external bypass path from said combination is selected when said bias current reaches a second predetermined level.

15. The cell balancing circuit as claimed in claim 14, wherein both said internal bypass path and said external bypass path from said combination are selected when said bias current reaches a third predetermined level.

16. A method for balancing a battery pack comprising:

receiving an enable signal for each cell of a plurality of cells for enabling a bypass current of each cell of said plurality of cells;

receiving a selection signal for each cell of said plurality of cells for selecting among a combination of an internal bypass path and an external bypass path for each cell of said plurality of cells;

generating a configuration signal for each cell of said plurality of cells for selectively conducting among said combination for each cell of said plurality of cells; and

conducting among said combination for each cell of said plurality of cells.

17. The method as claimed in claim 16, further comprising:

transmitting said selection signal over a serial control bus to each cell of said plurality of cells for selecting among said combination.

18. The method as claimed in claim 17, wherein said combination is selected from the group consisting of said internal bypass path, and said external bypass path.

19. The method as claimed in claim 16, further comprising:

generating a variable bias current to provide said selection signal for each cell of said plurality of cells for selecting among said combination.

20. The method as claimed in claim 19, wherein said combination is selected from the group consisting of said internal bypass path, said external bypass path, and paths including both internal bypass path and said external bypass path.

21. The method as claimed in claim 20, further comprising:

selecting said internal bypass path when said bias current reaches a first predetermined level.

22. The method as claimed in claim 21, further comprising:

selecting said external bypass path when said bias current reaches a second predetermined level.

23. The method as claimed in claim 22, further comprising:

selecting both said internal bypass path and said external bypass path when said bias current reaches a third predetermined level.

24. An electronic device comprising:

a plurality of cells of a battery pack;

a monitoring circuit for monitoring a voltage level of each cell of said plurality of cells and providing a monitoring signal for each cell of said plurality of cells representative of each said voltage level;

a processor for receiving each said monitoring signal, and providing an enable signal and a selection signal for each cell of said plurality of cells, wherein said enable signal representative of said voltage level of each cell of said plurality of cells greater than a first predetermined threshold or a voltage difference between said voltage level and a minimum of said voltage level greater than a second predetermined threshold; and

a cell balancing circuit for receiving each said enable signal and said selection signal, and balancing said plurality of cells, said cell balancing circuit comprising;

an internal bypass path for each cell of said plurality of cells;

an external bypass path for each cell of said plurality of cells;

a first input for receiving said enable signal from said processor for conducting bypass current for each cell of said plurality of cells;

a second input for receiving said selection signal from said processor for selecting among a combination of said internal bypass path and said external bypass path for each cell of said plurality of cells; and

a driving circuit for receiving said enable signal and said selection signal and for providing a configuration signal configured to selectively conduct among said combination of for each cell of said plurality of cells.

25. The electronic device as claimed in claim 24, wherein said combination is selected from the group consisting of said internal bypass path, said external bypass path, and paths including both internal bypass path and said external bypass path.

26. The electronic device as claimed in claim 24, wherein said combination is selected from the group consisting of said internal bypass path and said external bypass path.