Contactless interfacing of test signals with a device under test

• US 7,466,157 B2
• Filed: 02/05/2004
• Issued: 12/16/2008
• Est. Priority Date: 02/05/2004
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Primary Examiner(s): Nguyen; Ha
• Assistant Examiner(s): Chan; Emily Y
• Application Number:
  US10/772,970
• Publication Number:
  US 20050174131A1
• Time in Patent Office: 1,776 Days
• Field of Search: 324754-765, 257/48
• US Class Current: 324/750.3
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 1/07 Non contact-making probes
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT

Abstract

An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device.

Claims

1. A semiconductor wafer comprising:

a plurality of dies each comprising functional circuitry;

electrically conductive structures configured to contactlessly receive test signals from a test board in physical proximity to said wafer for testing said functional circuitry of said dies; and

an electrically conductive shielding plane disposed between at least part of ones of said conductive structures and at least part of said functional circuitry of said dies, said shielding plane shielding said dies from electrical interference.

2. The semiconductor wafer of claim 1, wherein each die comprises a set of said conductive structures.

3. The semiconductor wafer of claim 2, wherein each of said conductive structures in a set of said conductive structures are electrically connected to a plurality of said dies.

4. The semiconductor wafer of claim 1 further comprising a transmitter configured to transmit test signals on at least one of said conductive structures.

5. The semiconductor wafer of claim 4, wherein each of said dies comprises such a transmitter.

6. The semiconductor wafer of claim 1 further comprising a receiver configured to receive a test signal induced on at least one of said conductive structures.

7. The semiconductor wafer of claim 6, wherein each of said dies comprises such a receiver.

8. The semiconductor wafer of claim 1 further comprising a transceiver configured to transmit test signals on at least one of said conductive structures and to receive a test signal induced on at least one of said conductive structures.

9. The semiconductor wafer of claim 8, wherein each of said dies comprises such a transceiver.

10. The semiconductor wafer of claim 1 further comprising built in self test circuitry.

21. The semiconductor wafer of claim 1 further comprising:

a plurality of electrically conductive planes disposed between said conductive structures and said functional circuitry; and

insulating material disposed between said planes.

22. The semiconductor wafer of claim 21, wherein one of said planes is configured as a power distribution plane, and another of said planes is configured as a ground plane, wherein one of said power distribution plane or said ground plane comprises said shielding plane.

23. The semiconductor wafer of claim 1, wherein:

each die further comprises communications control circuitry; and

ones of said conductive structures are electrically connected to said communications control circuitry through openings in said plane.

24. The semiconductor wafer of claim 23, wherein at least one of said conductive structures is electrically connected at one end to said communications control circuitry and is electrically connected at another end to said plane.

25. The semiconductor wafer of claim 24, wherein said plane is a ground plane.

26. The semiconductor wafer of claim 23, wherein said communications control circuitry is configured to control communication of said test signals through said conductive structures to said test board, said communication control circuitry further configured to control communication of said test signals into and output of said functional circuitry of said die.

11. The semiconductor wafer of 1, wherein said electrically conductive shielding plane is sized to substantially cover said dies.

12. The semiconductor wafer of claim 11, wherein said shielding plane is a solid plate structure.

13. The semiconductor wafer of 1, wherein said shielding plane comprises openings through which said conductive structures are electrically connected to said functional circuitry of said dies.

14. A semiconductor wafer comprising:

a plurality of dies each comprising functional circuitry;

means for receiving test signals from ones of a plurality of tester channels on a test board in physical proximity to said wafer without physically contacting said tester channels; and

an electrically conductive shielding plane disposed between at least part of said means for receiving test signals and at least part of said functional circuitry of said dies, said shielding plane shielding said dies from electrical interference.

15. The semiconductor wafer of claim 14 further comprising means for sending test signals to ones of said tester channels without physically contacting said tester channels.

16. The semiconductor wafer of claim 14 further comprising means for controlling communications with said tester channels.

17. The semiconductor wafer of claim 14, wherein:

each die further comprises communications control circuitry; and

said means for receiving test signals is electrically connected to said communications control circuitry through openings in said plane.

18. The semiconductor wafer of claim 17, wherein said means for receiving test signals is electrically connected to said plane.

19. The semiconductor wafer of claim 18, wherein said plane is a ground plane.

20. The semiconductor wafer of claim 17, wherein said communications control circuitry is configured to control communication of said test signals through said conductive structures to said tester channels on said test board, said communication control circuitry further configured to control communication of said test signals into and output of said functional circuitry of said die.

27. The semiconductor wafer of claim 14 further comprising:

a plurality of electrically conductive planes disposed between said conductive structures and said functional circuitry; and

insulating material disposed between said planes.

28. The semiconductor wafer of claim 27, wherein one of said planes is configured as a power distribution plane, and another of said planes is configured as a ground plane, wherein one of said power distribution plane or said ground plane comprises said shielding plane.

29. The semiconductor wafer of 14, wherein said electrically conductive shielding plane is sized to substantially cover said dies.

30. The semiconductor wafer of claim 29, wherein said shielding plane is a solid plate structure.

31. The semiconductor wafer of 14, wherein said shielding plane comprises openings through which said means for receiving test signals is electrically connected to said functional circuitry of said at least one of said dies.