Asynchronous analog-to-digital converter and method

• US 7,466,258 B1
• Filed: 10/10/2006
• Issued: 12/16/2008
• Est. Priority Date: 10/07/2005
• Status: Expired due to Fees

• Current Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Original Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Inventors: Manohar, Rajit, Akopyan, Filipp, Apsel, Alyssa
• Primary Examiner(s): Nguyen; Khai M
• Application Number:
  US11/545,228
• Time in Patent Office: 798 Days
• Field of Search: 341/155, 341/159
• US Class Current: 341/155
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/0682 using a differential network structure, i.e. symmetrical with respect to ground
• CPC Class Codes: H03M 1/125 Asynchronous, i.e. free-running operation within each conversion cycle
• CPC Class Codes: H03M 1/361 having a separate comparator and reference value for each quantisation level, i.e. full flash converter type

Abstract

A method and apparatus for converting an analog input signal to a digital output signal, provide for simultaneously comparing the input signal to a sequential multiplicity of reference values representing a range of values of the input signal, and asynchronously processing digital results from simultaneous comparison to produce a digital representation of level crossings of the input signal with respect to the multiplicity of reference values.

Claims

1. An analog to digital converter for digitally representing the value of an input signal, comprising:

reference circuitry adapted for simultaneously providing three or more sequential reference values representing a range of values for the input signal;

a separate comparator representing each different reference value and coupled to receive its respective reference value at a first input thereof,

wherein each comparator includes a second input coupled to receive the input signal; and

asynchronous circuitry coupled to the separate comparators and adapted for digitally indicating the value of the input signal in response to level crossings between the input signal and the sequential reference values.

2. The converter of claim 1, further comprising a separate processing circuit coupled to an output of each comparator and adapted for using output signals from each respective comparator to provide a digital representation of level crossings between the input signal and each respective reference value.

3. The converter of claim 2, wherein each processing circuit includes a separate trigger circuit coupled to an output of its respective comparator and adapted to capture changes in the respective comparator output indicating a respective level crossing between the input signal and the respective reference value.

4. The converter of claim 3, wherein each processing circuit is adapted to determine if a change in a respective comparator output is a valid level crossing before providing a digital representation of a level crossing.

5. The converter of claim 4, wherein each processing circuit is adapted to store a logical indicator or token in response to a valid level crossing being determined for its respective comparator output.

6. The converter of claim 5, wherein each processing circuit is adapted to respond to a present signal from its respective trigger circuit indicating a respective present level crossing, to determine if an immediately previous valid level crossing was determined in either the present processing circuit or in processing circuits for respective reference levels located immediately above and below the present respective reference level.

7. The converter of claim 6, wherein each processing circuit is adapted to respond to a present signal from its respective trigger circuit indicating a respective present level crossing, by looking for the logical indicator or token first in the present processing circuit and then in processing circuits for respective reference levels located immediately above and below the present perspective reference level.

8. The converter of claim 6, wherein each processing circuit is adapted to process a present signal from its respective trigger circuit indicating a respective present level crossing as a valid level crossing and output a digital signal representing the level crossing indicated by the respective trigger circuit if an immediately previous valid level crossing was determined in either the present processing circuit or in processing circuits for respective reference levels located immediately above and below the present respective reference level.

9. The converter of claim 2, further comprising control circuitry coupled to said processing circuitry for providing power to only two comparators representing adjacent reference values immediately above and below a current value of the input signal.

10. The converter of claim 1, wherein the asynchronous circuit only provides digital output signals in response to changes in the input signal.

11. The converter of claim 1, wherein the asynchronous circuit only provides digital output signals in response to relative changes between the input signal and each of the reference values.

12. The converter of claim 1, wherein the reference circuitry is a capacitive voltage divider.

13. The converter of claim 1, wherein each comparator exhibits hysteresis.

14. A method for converting an analog input signal to a digital output signal, comprising the steps of:

simultaneously providing three or more sequential reference values representing a range of values for the input signal;

comparing the input signal to the three or more sequential reference values; and

asynchronously processing digital results from the step of comparing to produce a digital representation of level crossings of the input signal with respect to the three or more reference values, in response to each such level crossing.

15. The method of claim 14, wherein the step of comparing is performed using a separate comparator representing each reference level, and further comprising the step of capturing an output signal from each comparator indicating a respective level crossing between the input signal and the respective reference value, for enabling the step of asynchronously processing.

16. The method of claim 15, wherein the step of asynchronously processing is substantially performed by separate logic circuitry respective of each reference level and respective comparator.

17. The method of claim 16, wherein the step of asynchronously processing includes storing a variable indicating which reference level was last crossed by the input signal and whether the input signal is either above or below that last crossed reference level.

18. The method of claim 15, further comprising the step of providing power to only two separate comparators representing reference levels above and below the current input signal value.

19. The method of claim 16, wherein the step of asynchronously processing includes the step of determining if a change in a respective comparator output is a valid level crossing before producing a digital representation of that level crossing.

20. The method of claim 16, wherein the step of asynchronously processing includes the step of determining whether the input signal has crossed a respective reference level from below or from above.