Semiconductor memory device

• US 7,466,592 B2
• Filed: 08/20/2007
• Issued: 12/16/2008
• Est. Priority Date: 09/12/2003
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ogura, Taku, Yamauchi, Tadaaki, Mitani, Hidenori
• Primary Examiner(s): HUR, JUNG H
• Application Number:
  US11/892,055
• Publication Number:
  US 20080019184A1
• Time in Patent Office: 484 Days
• Field of Search: 365/185.03, 365/185.2, 365/185.21, 365/207, 365/210, 365/210.12, 365/210.14, 365/210.15, 365/210.1
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory cells aligned in rows and columns;

a plurality of word lines arranged corresponding to the memory cell rows, and connected to the memory cells in corresponding rows;

a circuit for generating a first voltage at a predetermined voltage level to be transmitted onto a selected word line in said plurality of word lines;

a division circuit for generating a plurality of divided voltages by dividing said first voltage;

a plurality of reference cells provided corresponding to the divided voltages and selectively rendered conductive in accordance with the respective divided voltages;

a reference voltage generation circuit for generating reference voltages in accordance with currents flowing through the respective reference cells; and

a sense amplifier circuit for generating a comparison reference current in accordance with a selected reference voltage among the reference voltages generated by said reference voltage generation circuit and comparing the comparison current with a current flowing through a selected memory cell to detect memory cell data in accordance with a result of comparison.

2. The semiconductor memory device according to claim 1, wherein

said reference cell is the same in structure as the memory cells and has a transistor structure having a control gate and a floating gate interconnected.

3. The semiconductor memory device according to claim 1, wherein

said reference cell includes an insulating gate type field effect transistor having a size set in accordance with a level of the reference voltage to be generated.