Reduced pin-count system interface for gigabit ethernet physical layer devices
First Claim
1. Apparatus for interfacing a media access controller (MAC) and a physical layer device (PHY) for operating as either a gigabit media independent interface or a ten bit interface, transferring data at a predetermined clock rate while substantially reducing the required number of input and output pins, said apparatus comprising:
- a multiplexer for mapping data and control signals that are normally applied to a predetermined number of pins to a lesser number of pins.
5 Assignments
0 Petitions
Accused Products
Abstract
A Gigabit Media Independent Interface (RGMII), which is adapted to also implement a ten bit interface (RTBI) that is intended to be an alternative to both the IEEE 802.3z GMII and the TBI is disclosed. The interface has a reduced number of input and output pins, i.e., pin-count, that can implement the above GMII and TBI standards. More particularly, the interface reduces the number of pins required to interconnect the MAC and the PHY from a maximum of 28 pins (TBI) to 13 pins in a cost effective and technology independent manner. The RGMII maps pins to transfer data at the same data rate with control functionality with a minimum number of input and output pins, and does so by utilizing both the rising and falling edges of the clock signal and complies with existing interface specifications set forth in the IEEE standards.
49 Citations
13 Claims
-
1. Apparatus for interfacing a media access controller (MAC) and a physical layer device (PHY) for operating as either a gigabit media independent interface or a ten bit interface, transferring data at a predetermined clock rate while substantially reducing the required number of input and output pins, said apparatus comprising:
a multiplexer for mapping data and control signals that are normally applied to a predetermined number of pins to a lesser number of pins. - View Dependent Claims (2, 3, 4, 5, 6)
-
7. Apparatus for interfacing a media access controller (MAC) and a physical layer device (PHY) for operating as at least one of a gigabit media independent interface and a ten bit interface, transferring data at a predetermined clock rate while substantially reducing the required number of input and output pins, said apparatus comprising:
-
a multiplexer for mapping data and control signals that are normally applied to a predetermined number of pins to a lesser number of pins; and six input pins for use in either the gigabit media independent interface operation or the ten bit interface operation in which; a transmit reference clock signal TXC is applied to a first pin in the gigabit media independent interface operation and the ten bit interface operation; 8 bits of data are applied to the second through fifth pins on both edges of a clock cycle during the gigabit media independent interface operation and the ten bit interface operation; 2 bits of data are applied to the sixth pin in the ten bit interface operation; and
,control signals are applied to the second through fifth pin in the gigabit media independent interface operation.
-
-
8. Apparatus for interfacing a media access controller (MAC) and a physical layer device (PHY) for operating as at least one of a gigabit media independent interface and a ten bit interface, transferring data at a predetermined clock rate while substantially reducing the required number of input and output pins, said apparatus comprising:
-
a multiplexer for mapping data and control signals that are normally applied to a predetermined number of pins to a lesser number of pins; and six output pins for use in either the gigabit media independent interface operation or the ten bit interface operation in which; a receive reference clock signal RXC is derived from the received data stream and appears on a first pin in the gigabit media independent interface operation and the ten bit interface operation; 8 bits of data are applied to the second through fifth pins on both edges of a clock cycle during the gigabit media independent interface operation and the ten bit interface operation; 2 bits of data are applied to the sixth pin in the ten bit interface operation; and
,control signals are applied to the second through fifth pin in the gigabit media independent interface operation.
-
- 9. A media interface for a media access controller (MAC) and a physical layer device (PHY) for operating as at least a gigabit media independent interface and a ten bit interface, which interface transfers data responsive to receiving a clock signal having a predetermined clock rate on a reduced number of pins, said interface multiplexing the data and control signals that are applied to the reduced number of pins using both edges of said clock signal and for selectively mapping the data and control signals to the reduced number of pins, wherein CRS and COL control signals are applied on a single pin.
-
11. A media interface for a media access controller (MAC) and a physical layer device (PHY) for operating as at least a gigabit media independent interface and a ten bit interface, which interface transfers data responsive to receiving a clock signal having a predetermined clock rate on a reduced number of pins, said interface multiplexing the data and control signals that are applied to the reduced number of pins using both edges of said clock signal and for selectively mapping the data and control signals to the reduced number of pins;
-
six input pins for use in either the gigabit media independent interface operation or the ten bit interface operation in which; a transmit reference clock signal TXC is applied to a first pin in the gigabit media independent interface operation and the ten bit interface operation; 8 bits of data are applied to the second through fifth pins on both edges of a clock cycle during the gigabit media independent interface operation and the ten bit interface operation; 2 bits of data are applied to the sixth pin in the ten bit interface operation; and
,control signals are applied to the second through fifth pin in the gigabit media independent interface operation.
-
-
12. A media interface for a media access controller (MAC) and a physical layer device (PHY) for operating as at least a gigabit media independent interface and a ten bit interface, which interface transfers data responsive to receiving a clock signal having a predetermined clock rate on a reduced number of pins, said interface multiplexing the data and control signals that are applied to the reduced number of pins using both edges of said clock signal and for selectively mapping the data and control signals to the reduced number of pins;
-
six output pins for use in either the gigabit media independent interface operation or the ten bit interface operation in which; a receive reference clock signal RXC is derived from the received data stream and appears on a first pin in the gigabit media independent interface operation and the ten bit interface operation; 8 bits of data are applied to the second through fifth pins on both edges of a clock cycle during the gigabit media independent interface operation and the ten bit interface operation; 2 bits of data are applied to the sixth pin in the ten bit interface operation; and
,control signals are applied to the second through fifth pin in the gigabit media independent interface operation.
-
-
13. A method of interfacing a media access controller (MAC) and a physical layer device (PHY) for operating either as a gigabit media independent interface or a ten bit interface, and transfer data at a predetermined rate while substantially reducing the required number of input and output pins, said method comprising:
-
multiplexing data and control signals using both edges of a clock signal having the predetermined rate; and
,strategically mapping the data and control signals that are normally applied to a predetermined number of pins to a significantly lesser number of pins while still maintaining the operability of the interface.
-
Specification