Memory efficient OFDM channel estimation and frequency domain diversity processing

• US 7,466,778 B2
• Filed: 12/21/2006
• Issued: 12/16/2008
• Est. Priority Date: 12/22/2005
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Kohli, Sanjai, Leimer, Donald, Sturza, Mark Alan, Ananth, Sharath
• Primary Examiner(s): Bocure; Tesfaldet
• Application Number:
  US11/614,590
• Publication Number:
  US 20070206687A1
• Time in Patent Office: 726 Days
• Field of Search: 375/267, 375/347, 375/316, 375/260, 455/132, 455/137
• US Class Current: 375/347
• CPC Class Codes: H04L 25/0232 by interpolation between sounding signals
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01

Abstract

A frequency domain diversity DVB receiver device includes multiple antenna ports for receiving radio signals, and radio signal processing circuits connected to the antenna ports that convert the received radio signals into digital samples. The digital samples from the different antenna ports time-share a front-end processor which processes the digital samples to provide time-domain symbols. The time-domain symbols are stored in time-domain symbol buffers according to which of the antenna ports the time-domain symbols are received. A fast fourier transform circuit then retrieves the time-domain symbols and converts them frequency-domain symbols, which are then stored one or more frequency-domain symbol buffers according to the antenna ports the corresponding radio signals are received. A diversity processor which combines the frequency-domain symbols from the frequency-domain symbol buffers.

Claims

1. A frequency domain diversity DVB receiver device comprising:

a. a first antenna port and a second antenna port for receiving radio signals;

b. a radio signal processing circuit connected to said first antenna port, and a second radio frequency signal processing circuit connected to said second antenna port, each radio signal processing circuit converting the radio signals to digital samples;

c. a first switch which alternately selects the digital samples of the first and the second radio signal processing circuits;

d. a front-end processor which processes the digital samples selected by said first switch to provide time-domain symbols;

e. a second switch synchronized with said first switch and connected to receive the output time-domain symbols of said front-end processor;

f. a first time-domain symbol buffer and a second time-domain symbol buffer receiving from said second switch to receive time-domain symbols corresponding to digital samples received from the first and second radio signal processing circuits, respectively;

g. a third switch which alternately receives time-domain symbols from said first and second time-domain symbol buffers;

h. a fast fourier transform circuit receiving the time-domain symbols from the said third switch and converting the time-domain symbols into frequency domain symbols;

i. a fourth switch synchronized with said third switch to receive the frequency domain symbols from the fast-fourier transform circuit;

j. a first frequency domain symbol buffer and a second frequency domain symbol buffer connected to said fourth switch to receive frequency domain symbols corresponding to time-domain symbols output from the first and second time-domain symbol buffers, respectively; and

k. a diversity processor which combines the frequency domain symbols from said first and second frequency-domain symbol buffers.

2. The device of claim 1, wherein said first antenna port and said second antenna port are connected to two spatially separated antennas.

3. The device of claim 1, wherein said first antenna port and said second antenna port are connected to two orthogonal polarization feeds from a single antenna.

4. The device of claim 1, wherein said first antenna port and said second antenna port are connected to two feeds from a single antenna providing different antenna patterns.

5. The device of claim 1, wherein said front-end processor implements cyclic delay diversity.

6. The device of claim 1, wherein said diversity processor implements path selection.

7. The device of claim 1, wherein said diversity processor implements equal-gain combining.

8. The device of claim 1, wherein said diversity processor implements maximal ratio combining.

9. A frequency domain diversity DVB receiver device comprising:

a. a first antenna port and a second antenna port for receiving radio signals;

b. a radio signal processing circuit connected to said first antenna port, and a second radio frequency signal processing circuit connected to said second antenna port, each radio signal processing circuit converting the radio signals to digital samples;

c. a first switch which alternately selects the digital samples of the first and the second radio signal processing circuits;

d. a front-end processor which processes the digital samples selected by said first switch to provide time-domain symbols;

e. a second switch synchronized with said first switch and connected to receive the output time-domain symbols of said front-end processor;

f. a first time-domain symbol buffer and a second time-domain symbol buffer receiving from said second switch to receive time-domain symbols corresponding to digital samples received from the first and second radio signal processing circuits, respectively;

g. a third switch which alternately receives time-domain symbols from said first and second time-domain symbol buffers;

h. a fast fourier transform circuit receiving the time-domain symbols from the said third switch and converting the time-domain symbols into frequency-domain symbols;

i. a multiplexer synchronized with said third switch connected to receive the frequency-domain symbols from said fast-fourier transform processor;

j. a frequency-domain symbol buffer connected to said multiplexer operating in one of a plurality of modes, each mode corresponding to a number of carrier included in each frequency-domain symbol used in that mode of operation; and

k. a diversity processor which processes the frequency-domain symbols of said frequency-domain symbol buffer.

10. The device of claim 9, wherein the modes of operation comprise an 8K mode, a 4K mode and a 2K mode.

11. The device of claim 10 wherein, under the 8K mode, the frequency-domain symbol buffer stores only frequency-domain symbols corresponding to time-domain symbols from a selected one of the first and second time-domain symbol buffers.

12. The device of claim 9, wherein the diversity processor sums frequency-domain symbols corresponding to time-domain symbols from both the first and second time-domain symbol buffers.

13. The device of claim 9, wherein the diversity processor selects only frequency-domain symbols corresponding to time-domain symbols from a selected one of the first and second time-domain symbol buffers.

14. The device of claim 9, wherein said first antenna port and said second antenna port are connected to two spatially separated antennas.

15. The device of claim 9, wherein said first antenna port and said second antenna port are connected to two orthogonal polarization feeds from a single antenna.

16. The device of claim 9, wherein said first antenna port and said second antenna port are connected to two feeds from a single antenna providing different antenna patterns.

17. The device of claim 9, wherein said front-end processor implements cyclic delay diversity.

18. The device of claim 9, wherein said diversity processor implements path selection.

19. The device of claim 9, wherein said diversity processor implements equal gain combining.

20. The device of claim 9, wherein said diversity processor implements maximal ratio combining.