PCI arbiter

• US 7,467,245 B2
• Filed: 07/22/2005
• Issued: 12/16/2008
• Est. Priority Date: 07/22/2005
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Metsker, Corey
• Primary Examiner(s): Rinehart; Mark
• Assistant Examiner(s): Cleary; Thomas J
• Application Number:
  US11/187,270
• Publication Number:
  US 20070022238A1
• Time in Patent Office: 1,243 Days
• Field of Search: 710/1, 710/22, 710/33, 710/107, 710/110, 710/111, 710/113, 710/114, 710/116, 710/243, 710/244, 710/310, 713/600, 370/447, 370/461, 370/463, 370/468, 455/450, 455/562.1
• US Class Current: 710/107
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data transfers with lower latency requirements. As an example, the arbiter closely manages all transactions and guarantees sufficient latencies by pre-empting lower-priority data transfers with higher priority data transfers. All devices on the bus are configured with a latency timer setting of zero or a non-zero value which guarantees required data transfer latencies are met which means that any device will terminate bus-master transfers quickly upon the bus grant signal being de-asserted. To ensure a transfer completes, bus grant for the priority transfer is asserted until entire data transfer completion is imminent, enabling transfers, such as high priority transfers, to complete uninterrupted.

Claims

1. A method for a bus arbiter to control access to a bus, comprising:

determining by a first device a first priority level of first data to be transferred by the first device, wherein the first priority is based on a latency requirement of a first type of data corresponding to the first data;

determining by a second device a second priority level of second data to be transferred by the second device, wherein the second priority level is based on a latency requirement of a second type of data corresponding to the second data;

receiving a first bus access request from a first device requesting access to the bus for transferring the first data;

receiving data representative of the first priority for the first data corresponding to the first bus access request separately from the first bus access request;

asserting a first bus grant corresponding to the first bus access request to the first device until an entire packet transfer completion is imminent unless a bus access request is received with a higher priority level;

receiving a second bus access request from the second device for transferring the second data;

,

receiving data representative of the second priority level for the second data separately from the first bus access request, the data representative of the priority of the first data, and the second bus access request, wherein the second priority level is a higher priority than the first priority level;

immediately de-asserting the first bus grant associated with the first bus access request responsive to the second bus access request having a higher priority than the bus access request; and

asserting a second bus grant associated with the second bus access request signal to the second device responsive to the second bus access request having a higher priority than the bus access request;

wherein the first device is responsive to the de-asserting of the first bus grant to immediately relinquish the bus.

2. The method according to claim 1, wherein the data representative of the first priority is acquired from a signal received on an unused bus line.

3. The method according to claim 1, wherein the data representative of a first priority level is acquired from a signal received external to the bus.

4. The method according to claim 1, further comprising:

setting a latency timer to zero.

5. The method according to claim 1, further comprising:

determining a third priority level corresponding to a type of data for a third data to be transferred

setting a latency timer to zero;

receiving a third bus access request after the second bus access request;

receiving data representative of the third priority level corresponding to the third bus access request separately from the third bus access request, wherein the third priority level is a lower priority than the second priority level corresponding to the second bus access request;

maintaining the second bus grant associated with the second bus access request until a transfer associated with the second bus access request is completed, and then de-asserting the second bus grant associated with the second bus access request; and

asserting a third bus grant associated with the third bus access request signal after de-asserting the second bus grant to the second device.

6. The method according to claim 1, further comprising:

masking a second bus access request that has a lower priority until a transfer associated with the bus access request has completed.

7. The method according to claim 1 wherein the bus is one of the group consisting of a PCI version 3.0 compliant bus, a PCI version 2.0 compliant bus, a PCI version 2.1 compliant bus, a PCI version 2.2 complaint bus, a PCI version 2.3 compliant bus a PCI version 1.0 compliant bus, a miniPCl compliant bus and a CardBus compliant bus.

8. A system, comprising:

a bus arbiter coupled to a bus for controlling access to the bus, wherein the bus is coupled to a first device and a second device;

at least one coupler between the bus arbiter and the first device for asserting at least one of the group consisting of a bus access request signal and a bus grant signal between the bus arbiter and the first device;

at least one coupler between the bus arbiter and the second device for asserting at least one of the group consisting of a bus access request signal and a bus grant signal between the bus arbiter and the second device;

a first additional coupler for coupling the bus arbiter to the first device enabling the bus arbiter to receive a signal indicative of a first priority level corresponding to first data associated with a first bus access request from the first device separately from the bus access request from the first device; and

a second additional coupler for coupling the bus arbiter to the second device enabling the bus arbiter to receive a signal indicative of a second priority level corresponding to a second data associated with a second bus access request from the second device separately from the bus access request from the second device;

wherein the bus arbiter sets a latency timer for the first device and a latency timer for the second device to zero;

wherein the bus arbiter is responsive to a bus access request signal from the first device to assert and hold bus grant to the first device while data the first data is being transferred;

wherein the bus arbiter is responsive to receiving a second bus access request on the at least one coupler between the bus arbiter and the second device and a separate signal indicative of a second priority level corresponding to the second data being transferred associated with the second bus access request on the additional coupler for coupling the bus arbiter to the second device, wherein the arbiter is configured to immediately de-assert bus grant to the first device, and assert a bus grant to the second device responsive to the second priority level being higher than the first priority level;

wherein the first priority level is based on a latency requirement of the first data and the second priority level is based on a latency requirement of the second data; and

wherein the first device relinquishes the bus immediately responsive to the first bus grant being de-asserted.

9. The system according to claim 8, further comprising a circuit for masking a subsequent bus access request for data that has a lower priority from the bus arbiter until a transfer associated with the first bus access request from the first device has completed.

10. The system according to claim 8, wherein the bus is one of the group consisting of a PCI version 3.0 compliant bus, a PCI version 2.0 compliant bus, a PCI version 2.1 compliant bus, a PCI version 2.2 complaint bus, a PCI version 2.3 compliant bus a PCI version 1.0 compliant bus, a miniPCl compliant bus and a CardBus compliant bus.

11. A multi-transceiver system, comprising:

a first wireless transceiver, the first wireless transceiver further comprising a latency timer;

a second wireless transceiver, the second wireless transceiver further comprising a latency timer;

a host unit comprising a host memory for storing packets for the first wireless transceiver and the second wireless transceiver;

a bus coupling the host memory to the first wireless transceiver and the second wireless transceiver; and

a bus arbiter for controlling access to the bus, the bus arbiter coupled to the host unit, first wireless transceiver and second wireless transceiver;

a first digital output coupling the first wireless transceiver to the bus arbiter;

a second digital output coupling the second wireless transceiver to the bus arbiter;

wherein the bus arbiter sets a latency timer for the first wireless transceiver and the latency timer for the second wireless transceiver to zero

wherein the bus arbiter is configured to grant a bus access request to the first wireless transceiver;

wherein the bus arbiter is configured to determine a first priority level for the bus access request form the first wireless device based on a separate signal received on the first digital output from the first wireless device;

wherein the bus arbiter is configured to immediately de-assert bus grant to the first wireless transceiver responsive to determining that a bus access request from the second wireless transceiver is for data that has a higher priority than data corresponding to the bus access request from the first wireless transceiver;

wherein the first wireless transceiver is responsive to the latency timer being set to zero to relinquish the bus immediately after the bus arbiter de-asserts bus grant;

wherein the first wireless device bases the first priority level on a latency requirement of data associated with the first bus access request; and

wherein the second wireless device bases the second priority level on a latency requirement of data associated with the second bus access request.

12. The multi-transceiver system according to claim 11, further comprising:

the host unit further comprising a buffer coupled to the bus;

wherein the host unit does not indicate it is ready to send the packet until the packet is transferred from the host memory to the buffer.

13. The multi-transceiver system according to claim 12, further comprising:

a central processing unit; and

a PCI version 3.0 compliant bus, a PCI version 2.0 compliant bus, a PCI version 2.1 compliant bus, a PCI version 2.2 complaint bus, a PCI version 2.3 compliant bus a PCI version 1.0 compliant bus, a miniPCl compliant bus and a CardBus compliant bus.

14. The multi-transceiver system according to claim 13, further comprising an interface to a distribution system;

wherein the interface receives the packet from the distribution system and stores the packet in the host memory.