Method and apparatus for vector table look-up

• US 7,467,287 B1
• Filed: 12/31/2001
• Issued: 12/16/2008
• Est. Priority Date: 12/31/2001
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Bratt, Joseph P., Trivedi, Sushma Shrikant
• Primary Examiner(s): Li; Aimee J
• Application Number:
  US10/038,478
• Time in Patent Office: 2,542 Days
• Field of Search: 712/4
• US Class Current: 712/4
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

Methods and apparatuses for performing vector table look-up using multiple look-up tables. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a plurality of numbers; partitioning look-up memory into a plurality of look-up tables; looking up simultaneously a plurality of elements from the plurality of look-up tables. Each of the plurality of elements is in one of the plurality of look-up tables and is pointed to by one of the plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.

Claims

1. A method for execution by a microprocessor in response to receiving a single instruction, the method comprising:

receiving the single instruction that includes a first index of a first vector in a first entry in a register file and a second index of a second vector in a second entry in the register file,

receiving the first vector having a first plurality of numbers and the second vector having a second plurality of numbers, each of the first plurality of numbers pointing to one of a plurality of entries, each of the plurality of entries being in one of a plurality of look-up tables; and

replacing simultaneously the plurality of entries in the plurality of look-up tables that are indicated by the first plurality of numbers from the first entry in the register file, with the second plurality of numbers from the second entry in the register file;

wherein the receiving and the replacing operations are performed in response to the microprocessor receiving the single instruction;

wherein the microprocessor comprises a media processor integrated with a memory controller for host memory on a single integrated circuit.

2. A method as in claim 1 wherein the single instruction specifies indices of the first and second entries in the register file.

3. A method for execution by a microprocessor in response to receiving a single instruction, the method comprising:

receiving the single instruction having an identity number code that specifies a DMA controller and an index of a first entry in a register file, wherein the first entry register file contains control parameters that include a bit segment which specifies a count indicating a number of entries to be loaded in each of a plurality of look-up units;

receiving the control parameters from the register file; and

replacing at least one entry in at least one of the plurality of look-up units in a microprocessor unit according to the control parameters with at least one number using the Direct Memory Access (DMA) controller;

wherein the replacing is performed in response to the microprocessor receiving the single instruction.

4. A method for execution by a microprocessor in response to receiving a single instruction, the method comprising:

receiving the single instruction having an identity number code that specifies a DMA controller and an index of a first entry in a register file, wherein the first entry in the register file contains control parameters, wherein the control parameters include a bit segment which specifies a count indicating a number of entries to be loaded in each of a plurality of look-up units; and

receiving the control parameters from the register file;

replacing at least one entry for each of a plurality of look-up units in a microprocessor according to the control parameters, with a plurality of numbers using the Direct Memory Access (DMA) controller;

wherein the replacing is performed in response to the microprocessor receiving the single instruction.

5. A method as in claim 4 wherein a single index encoded in the instruction specifies a location of the at least one entry in the plurality of look-up units.

6. A method as in claim 4 wherein a single index encoded in the instruction specifies a total number of the at least one entry for each of a plurality of look-up units.

7. A method as in claim 4 wherein a source address of the plurality of numbers in host memory is specified in an entry of a register file.

8. A method as in claim 7 wherein the single instruction specifies an index of the entry in the register file.

9. A method as in claim 4 wherein the at least one entry for each of the plurality of look-up units comprises a plurality of entries for each of the plurality of look-up units.

10. A method for execution by a microprocessor in response to receiving a single instruction, the method comprising:

receiving the single instruction that includes a first index of a first vector in a first entry in a register file and a second index of a second vector in a second entry in the register file;

receiving the first vector having a plurality of numbers from the register file;

partitioning a look-up memory into a first plurality of look-up tables, wherein the look-up memory comprises a second plurality of look-up units, and wherein the partitioning of the look-up memory comprises configuring the second plurality of look-up units into the first plurality of look-up tables according to a configuration indicator specified by the single instruction;

looking up simultaneously a plurality of elements of the second vector from the first plurality of look-up tables, each of the plurality of elements being in one of the first plurality of look-up tables and being pointed to by one of the plurality of numbers;

wherein the partitioning and the looking-up operations are performed in response to the microprocessor receiving the single instruction.

11. A method as in claim 10 wherein the receiving the first vector having a plurality of numbers comprises:

partitioning a string of bits into a plurality of segments to generate the plurality of numbers.

12. A method as in claim 11 wherein the single instruction specifies format information in which the plurality of numbers are stored in the string of bits.

13. A method as in claim 11 wherein the string of bits is received from an entry of a register file.

14. A method as in claim 13 wherein the single instruction specifies an index of the entry.

15. A method as in claim 10 further comprising:

storing the second vector having the plurality of elements in an entry of a register file.

16. A method as in claim 15 wherein the single instruction specifies an index of the entry.

17. A method as in claim 15 wherein the single instruction specifies format information in which the plurality of elements are stored in the entry.

18. A method as in claim 10, wherein the look-up memory comprises a plurality of look-up units, and wherein said partitioning look-up memory comprises

configuring the plurality of look-up units into the plurality of look-up tables;

wherein each of the plurality of look-up units comprises 256 8-bit entries.

19. A method as in claim 10 wherein the single instruction specifies a total number of entries contained in each of the plurality of look-up tables.

20. A method as in claim 19 wherein the total number of entries is one of:

a) 256;

b) 512; and

c) 1024.

21. A method as in claim 19 wherein the total number of bits is one of:

a) 8;

b) 16; and

c) 24.

22. A method as in claim 10 wherein the single instruction specifies a total number of bits used by each entry contained in the plurality of look-up tables.

23. A method as in claim 10 wherein the microprocessor comprises a media processor integrated with a memory controller for host memory on a single integrated circuit.

24. A machine readable media containing an executable computer program instruction which when executed by a digital processing system causes said system to perform a method comprising:

receiving a single instruction that includes a first index of a first vector in a first entry in a register file and a second index of a second vector in a second entry in the register file,

receiving the first vector having a first plurality of numbers and a second vector having a second plurality of numbers, each of the first plurality of numbers pointing to one of a plurality of entries, each of the plurality of entries being in one of a plurality of look-up tables; and

replacing simultaneously the plurality of entries in the plurality of look-up tables that are indicated by the first plurality of numbers from the first entry in the register file with the second plurality of numbers from the second entry in the register file;

wherein the receiving and the replacing operations are performed in response to the microprocessor receiving the single instruction;

wherein the microprocessor comprises a media processor integrated with a memory controller for host memory on a single integrated circuit.

25. A media as in claim 24 wherein the single instruction specifies indices of the first and second entries in the register file.

26. A machine readable media containing an executable computer program instruction which when executed by a digital processing system causes said system to perform a method comprising:

receiving the single instruction having an identity number code that specifies a DMA controller and an index of a first entry in a register file, wherein the first entry in the register file contains control parameters that include a bit segment which specifies a count indicating a number of entries to be loaded in each of a plurality of look-up units;

receiving the control parameters from the register file; and

replacing at least one entry in at least one of a plurality of look-up units in a microprocessor unit according to the control parameters with at least one number using a Direct Memory Access (DMA) controller;

wherein the replacing is performed in response to the microprocessor receiving the single instruction.

27. A machine readable media containing an executable computer program instruction which when executed by a digital processing system causes said system to perform a method comprising:

receiving the single instruction having an identity number code that specifies a DMA controller and an index of a first entry in a register file, wherein the first entry in the register file contains control parameters, wherein the control parameters include a bit segment which specifies a count indicating a number of entries to be loaded in each of a plurality of look-up units;

receiving the control parameters from the register file; and

replacing at least one entry for each of a plurality of look-up units in a microprocessor according to the control parameters, with a plurality of numbers using a Direct Memory Access (DMA) controller;

wherein the receiving is performed in response to the microprocessor receiving the single instruction.

28. A media as in claim 27 wherein a single index encoded in the instruction specifies a location of the at least one entry in the plurality of look-up units.

29. A media as in claim 27 wherein a single index encoded in the instruction specifies a total number of the at least one entry for each of a plurality of look-up units.

30. A media as in claim 27 wherein a source address of the plurality of numbers is specified in an entry of a register file.

31. A media as in claim 30 wherein the single instruction specifies an index of the entry in the register file.

32. A machine readable media containing an executable computer program instruction which when executed by a digital processing system causes said system to perform a method comprising:

receiving a single instruction that includes a first index of a first vector in a first entry in a register file and a second index of a second vector in a second entry in the register file;

receiving the first vector having a plurality of numbers from the register file;

partitioning a look-up memory into a first plurality of look-up tables, wherein the look-up memory comprises a second plurality of look-up units, and wherein the partitioning of the look-up memory comprises configuring the second plurality of look-up units into the first plurality of look-up tables according to a configuration indicator specified by the single instruction;

looking up simultaneously a plurality of elements of the second vector from the first plurality of look-up tables, each of the plurality of elements being in one of the first plurality of look-up tables and being pointed to by one of the plurality of numbers;

wherein the partitioning and the looking-up operations are performed in response to the microprocessor receiving the single instruction.

33. A media as in claim 32 wherein said receiving the first vector having a plurality of numbers comprises:

partitioning a string of bits into a plurality of segments to generate the plurality of numbers.

34. A media as in claim 33 wherein the single instruction specifies format information in which the plurality of numbers are stored in the string of bits.

35. A media as in claim 33 wherein the string of bits is received from an entry of a register file.

36. A media as in claim 35 wherein the single instruction specifies an index of the entry.

37. A media as in claim 32 wherein the method further comprises:

storing the second vector having the plurality of elements in an entry of a register file.

38. A media as in claim 37 wherein the single instruction specifies an index of the entry.

39. A media as in claim 37 wherein the single instruction specifies format information in which the plurality of elements are stored in the entry.

40. A media as in claim 32 wherein the single instruction specifies a total number of entries contained in each of the plurality of look-up tables.

41. A media as in claim 40 wherein the total number of entries is one of:

a) 256;

b) 512; and

c) 1024.

42. A media as in claim 32 wherein the single instruction specifies a total number of bits used by each entry contained in the plurality of look-up tables.

43. A media as in claim 42 wherein the total number of bits is one of:

a) 8;

b) 16; and

c) 24.

44. A media as in claim 32 wherein each of the plurality of look-up units comprises 256 8-bit entries.