Arrangement and method for controlling communication of data between processors

• US 7,467,312 B2
• Filed: 09/30/2005
• Issued: 12/16/2008
• Est. Priority Date: 09/30/2004
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Esch, Michael, Rost, Astrid
• Primary Examiner(s): Suryawanshi; Suresh K
• Application Number:
  US11/240,815
• Publication Number:
  US 20060069934A1
• Time in Patent Office: 1,173 Days
• Field of Search: 713/320, 713/323
• US Class Current: 713/320
• CPC Class Codes: H04W 52/0274 by switching on or off the equipment or parts thereof
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The communication of data between two coupled processors is controlled using a ready-to-receive signal which is provided by the first processor such that it has an activated signal level or a deactivated signal level and which is used to indicate to the second processor that the first processor is or is not ready to receive data. The second processor is able to change from the awake state to a sleep state and to change back from the sleep state to the awake state. The second processor detects when the first processor changes the ready-to-receive signal from the deactivated signal level to the activated signal level while the second processor is in the sleep state and, in this case, determines that the changing of the ready-to-receive signal is a request to change to the awake state.

Claims

1. A method for controlling communication of data between a first processor and a second processor which is coupled to the first processor, the method comprising:

the first processor providing a ready-to-receive signal having an activated signal level or a deactivated signal level, which signal is used to indicate to the second processor that the first processor is or is not ready to receive data;

the second processor being able to change from an awake state to a sleep state and to change back from the sleep state to the awake state; and

the second processor detecting when the first processor changes the ready-to-receive signal from the deactivated signal level to the activated signal level while the second processor is in the sleep state and, in this case, determining that the changing of the ready-to-receive signal is a request for the second processor to change to the awake state.

2. The method as claimed in claim 1, wherein, when the first processor changes the ready-to-receive signal from the deactivated signal level to the activated signal level while the second processor is in the awake state and there are no data due to be sent by the second processor, the second processor determines that the changing of the ready-to-receive signal is a request to prepare to receive data.

3. The method as claimed in claim 1, further comprising:

the second processor providing a ready-to-receive signal having an activated signal level or a deactivated signal level, which signal is used to indicate to the first processor that the second processor is or is not ready to receive data;

the first processor being able to change from the awake state to a sleep state and to change back from the sleep state to the awake state;

the first processor detecting when the second processor changes the ready-to-receive signal from the deactivated signal level to the activated signal level while the first processor is in the sleep state and, in this case, determining that the changing of the ready-to-receive signal is a request to change to the awake state; and

/or

when the second processor changes the ready-to-receive signal from the deactivated signal level to the activated signal level while the first processor is in the awake state and there are no data due to be sent by the first processor, the first processor determining that the changing of the ready-to-receive signal is a request to prepare to receive data.

4. The method as claimed in claim 1, wherein a ready-to-receive signal is transmitted using a ready-to-send or clear-to-send line for data flow control in accordance with the V.24 interface protocol.

5. The method as claimed in claim 1, wherein the first processor is a modem processor and the second processor is an application processor.

6. The method as claimed in claim 1, wherein the first processor is an application processor and the second processor is a modem processor.

7. The method as claimed in claim 1, wherein the first processor and/or the second processor is/are contained in a mobile radio telephone.

13. The method as claimed in claim 1, further comprising:

the first processor changing the ready-to-receive signal from the activated signal level to the deactivated signal level, thereby indicating an overflow situation; and

the second processor interrupting data transmission in response to the changing of the ready-to-receive signal from the activated signal level to the deactivated signal level.

8. A dual-processor arrangement comprising:

a first processor and a second processor;

a data output of the first processor being coupled to a data input of the second processor and

a data output of the second processor being coupled to a data input of the first processor; and

a control signal output of the first processor being coupled to a control signal input of the second processor,

wherein the first processor is set up to provide a ready-to-receive signal having an activated signal level or a deactivated signal level, which signal is used to indicate to the second processor that the first processor is or is not ready to receive data,

wherein the second processor has a state control unit which is set up to change the second processor from an awake state to a sleep state and to change it back from the sleep state to the awake state, and

wherein the second processor has a monitoring unit which is set up to detect when the first processor changes the ready-to-receive signal from the deactivated signal level to the activated signal level while the second processor is in the sleep state and, in this case, the state control unit is set up to determine that the changing of the ready-to-receive signal is a request to change the second processor to the awake state.

9. The dual-processor arrangement as claimed in claim 8, wherein the first processor is a modem processor and the second processor is an application processor.

10. The dual-processor arrangement as claimed in claim 8, wherein the first processor is an application processor and the second processor is a modem processor.

11. The dual-processor arrangement as claimed in claim 8, wherein, when the first processor changes the ready-to-receive signal from the deactivated signal level to the activated signal level while the second processor is in the awake state and there are no data due to be sent by the second processor, the second processor is set up to determine that the changing of the ready-to-receive signal is a request to prepare to receive data.

12. A mobile radio telephone having a dual-processor arrangement as claimed in claim 8.

14. The dual-processor arrangement of claim 8, wherein:

the first processor is further set up to change the ready-to-receive signal from the activated signal level to the deactivated signal level, thereby indicating an overflow situation; and

the monitoring unit of the second processor is further set up to detect when the first processor changes the ready-to-receive signal from the activated signal level to the deactivated signal level, and to interrupt data transmission in response to thereto.