Strained silicon on a SiGe on SOI substrate

• US 7,468,538 B2
• Filed: 02/22/2005
• Issued: 12/23/2008
• Est. Priority Date: 11/13/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Chidambarrao, Dureseti
• Primary Examiner(s): Garber; Charles D.
• Assistant Examiner(s): Isaac; Stanetta D
• Application Number:
  US11/061,444
• Publication Number:
  US 20050142700A1
• Time in Patent Office: 1,400 Days
• Field of Search: 257/347, 257/522, 257/E23.013, 257/E29.295, 257/E29.298, 257/288
• US Class Current: 257/347
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

An intermediate semiconductor structure is disclosed. The semiconductor structure includes a substrate; a relaxed Si_1-xGe_x layer on the substrate, the relaxed Si_1-xGe_x layer having at least one trench; an un-etched Si layer portion on the substrate and beneath the relaxed Si_1-xGe_x layer along a periphery of the substrate providing structural support for the relaxed Si_1-xGe_x layer along the periphery of the substrate; and at least one void between the relaxed Si_1-xGe_x layer and the substrate, wherein the void encompasses an entire surface area of the substrate but for a portion of the substrate in contact with the un-etched Si layer portion.

Claims

1. An intermediate semiconductor structure comprising:

a substrate;

a relaxed Si_1-xGe_x layer on the substrate, the relaxed Si_1-xGe_x layer having at least one trench;

an un-etched Si layer portion on the substrate and beneath the relaxed Si_1-xGe_x layer alone a periphery of the substrate providing structural support for the relaxed Si_1-xGe_x layer along the periphery of the substrate; and

at least one void between the relaxed Si_1-xGe_x layer and the substrate, wherein the at least one void encompasses an entire surface area of the substrate but for a portion of the substrate in contact with the un-etched Si layer portion.

2. An intermediate semiconductor structure according to claim 1, wherein the substrate is comprised of a silicon-on-insulator wafer.

3. An intermediate semiconductor structure according to claim 1, wherein the thickness of the Si_1-xGe_x layer is less than a critical thickness for the Si_1-xGe_x layer.

4. An intermediate semiconductor structure according to claim 1, further comprising a strained semiconductor layer epitaxially grown on the relaxed Si_1-xGe_x layer.

5. An intermediate semiconductor structure according to claim 4, wherein the strained semiconductor layer is comprised of Si.

6. An intermediate semiconductor structure according to claim 4, wherein the strained semiconductor layer is comprised of Si_1-yC_y.