Multiple chips bonded to packaging structure with low noise and multiple selectable functions

• US 7,468,551 B2
• Filed: 05/13/2003
• Issued: 12/23/2008
• Est. Priority Date: 05/19/2000
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Peng, Bryan
• Primary Examiner(s): Williams; Alexander O
• Application Number:
  US10/437,333
• Publication Number:
  US 20030201545A1
• Time in Patent Office: 2,051 Days
• Field of Search: 257/700, 257/701, 257/758, 257/686, 257/685, 257/723, 257/777, 257/778, 257/737, 257/734, 257/738, 257/698, 257/695, 257/202, 257/204, 257/208, 257/210, 257/281, 257/724, 257/528, 257/532, 257/E25.013, 257/E25.011, 257/E25.03, 257/784, 257/773, 257/696, 257/781, 257/779, 257/786, 257/E23.079
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Claims

1. A chip package comprising:

a circuit component;

a first chip connected to said circuit component, wherein said first chip has multiple first bit-width options, wherein said multiple first bit-width options comprise a x8 option;

multiple first metal bumps connecting said first chip to said circuit component, wherein said first chip is connected to said circuit component in a flip-chip assembly; and

a second chip connected to said circuit component, wherein said second chip has multiple second bit-width options.

2. The chip package of claim 1, wherein said circuit component comprises a substrate.

3. The chip package of claim 1 further comprising multiple second metal bumps connecting said second chip to said circuit component, wherein said second chip is connected to said circuit component in a flip-chip assembly.

4. The chip package of claim 1, wherein said multiple first bit-width options further comprise a x4 option.

5. The chip package of claim 1, wherein said multiple second bit-width options comprise a x4 option.

6. The chip package of claim 1, wherein said multiple second bit-width options comprise a x8 option.

7. The chip package of claim 1, wherein said multiple first bit-width options further comprise a x16 option.

8. The chip package of claim 1 wherein said multiple second bit-width options comprise a x16 option.

9. The chip package of claim 1 further comprising a capacitor over said circuit component.

10. The chip package of claim 9, wherein said capacitor comprises a first terminal connected to a power plane of said circuit component and a second terminal connected to a ground plane of said circuit component.

11. The chip package of claim 1, wherein said circuit component comprises a control terminal connecting said first and second chips.

12. The chip package of claim 11, wherein said control terminal comprises solder.

13. The chip package of claim 1, wherein said circuit component comprises a selection terminal connecting said first and second chips.

14. The chip package of claim 13, wherein said selection terminal comprises solder.