Configurable integrated circuit with offset connections
First Claim
Patent Images
1. An integrated circuit (“
- IC”
) comprising;
a set of at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and
a plurality of direct offset connections, wherein each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array, wherein at least one direct offset connection of said plurality of direct offset connections comprises an intervening buffer circuit but does not comprise an intervening routing circuit, and wherein said intervening buffer circuit is not inside either of said two offset nodes.
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Abstract
Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.
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Citations
20 Claims
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1. An integrated circuit (“
- IC”
) comprising;a set of at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and a plurality of direct offset connections, wherein each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array, wherein at least one direct offset connection of said plurality of direct offset connections comprises an intervening buffer circuit but does not comprise an intervening routing circuit, and wherein said intervening buffer circuit is not inside either of said two offset nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- IC”
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11. An electronic device comprising an integrated circuit (IC), said IC comprising:
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a set of at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and a plurality of direct offset connections, wherein each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array, wherein at least one direct offset connection of said plurality of direct offset connections comprises an intervening buffer circuit but does not comprise an intervening routing circuit, and wherein said intervening buffer circuit is not inside either of said two offset nodes. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification