Programming method for flash memory capable of compensating reduction of read margin between states due to hot temperature stress

• US 7,468,907 B2
• Filed: 09/18/2006
• Issued: 12/23/2008
• Est. Priority Date: 01/12/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Dong-Ku, Lim, Young-Ho
• Primary Examiner(s): Lam; David
• Application Number:
  US11/522,406
• Publication Number:
  US 20070159889A1
• Time in Patent Office: 827 Days
• Field of Search: 365/185.03, 365/185.22, 365/185.21, 365/185.24, 365/185.28, 365/185.02
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of states. The program method includes programming memory cells selected to have one of the states by using multi-bit data; detecting programmed memory cells within a predetermined region of a threshold voltage distribution where the programmed memory cells having the respective states are distributed, wherein the predetermined region of the respective states is selected by one of a first verify voltage and a read voltage and a second voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

Claims

1. A programming method for a flash memory device having a plurality of memory cells storing multi-bit data indicating one of a plurality of states, the programming method comprising:

programming memory cells selected to have one of the plurality of states using multi-bit data;

detecting programmed memory cells within a predetermined region of a threshold voltage distribution, wherein the programmed memory cells have one of the plurality of states,

wherein the predetermined region is selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and

programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to the respective states.

2. The programming method of claim 1, wherein first verify voltages corresponding to the respective ones of the plurality of states are used to determine whether the selected memory cells are programmed using multi-bit data.

3. The programming method of claim 1, wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to the respective states, program voltages applied to selected word lines vary with the states.

4. The programming method of claim 3, wherein the program voltage increases incrementally with repetition of a programming loop.

5. The programming method of claim 4, wherein the increment of the program voltage is maintained irrespective of the states.

6. The programming method of claim 4, wherein the increment of the program voltage is variable with the states.

7. The programming method of claim 1, wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to the respective states, program voltages applied to selected wordlines are equivalent to one another irrespective of the states.

8. A programming method for a flash memory device having a plurality of memory cells storing multi-bit data indicating one of first through fourth states, the programming method comprising:

programming memory cells selected to have one of the states using multi-bit data;

detecting programmed memory cells within a predetermined region of a threshold voltage distribution where the programmed memory cells having one of the first through fourth states are distributed,

wherein the predetermined region is selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and

programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

9. The programming method of claim 8, wherein the first state represents an erased state, and the detected memory cells store the second state.

10. The programming method of claim 9, further comprising:

detecting programmed memory cells arranged within a predetermined region of a threshold voltage distribution where the programmed memory cells of the third state are distributed,

wherein the predetermined region of the third state is selected by either one of a first verify voltage and a read voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and

programming the detected memory cells to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to the third state.

11. The programming method of claim 10, further comprising:

detecting programmed memory cells arranged within a predetermined region of a threshold voltage distribution where programmed memory cells of the fourth state are distributed,

wherein the predetermined region of the fourth state is selected by either one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and

programming the detected memory cells to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to the fourth state.

12. The programming method of claim 11, wherein first verify voltages corresponding to the second through fourth states are used to determine whether the selected memory cells are programmed using multi-bit data.

13. The programming method of claim 12, wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to the respective states, program voltages applied to selected word lines vary with the states.

14. The programming method of claim 13, wherein the program voltage increases incrementally with repetition of a programming loop.

15. The programming method of claim 14, wherein the increment of the program voltage is maintained irrespective of the second to fourth states.

16. The programming method of claim 14, wherein the increment of the program voltage is variable with the second to fourth states.

17. The programming method of claim 12, wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to the respective states, program voltages applied to selected wordlines are equivalent to one another irrespective of the states.