Apparatus and method for dynamically repairing a semiconductor memory

• US 7,468,922 B2
• Filed: 04/24/2007
• Issued: 12/23/2008
• Est. Priority Date: 07/18/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Callaway, Brian P., Baum, Aaron M.
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/789,663
• Publication Number:
  US 20070195623A1
• Time in Patent Office: 609 Days
• Field of Search: 365/189.01, 365/201, 365/200, 365/189.07
• US Class Current: 365/189.011
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 2029/4002 Comparison of products, i.e. test results of chips or with golden chip
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/28 Dependent multiple arrays, e.g. multi-bit arrays
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements when errors are detected. Unused spare memory elements are remapped utilizing a circuit that overrides unblown fuses or antifuses.

Claims

1. A method of testing memory for faults, comprising

writing a string of bits to a first collection of memory bits and a second collection of memory bits;

reading a first string of read bits from the first collection of memory bits;

reading a second string of read bits from the second collection of memory bits; and

comparing each bit in the first string of read bits with a corresponding one in the second string of read bits.

2. The method of claim 1, further comprising determining that a fault has occurred in at least one of the first collection of memory bits and the second collection of memory bits when at least one of the first string of read bits differs from a corresponding read bit of the second string of read bits.

3. The method of claim 1, further comprising writing a string of bits to a third collection of memory bits, reading a third string of read bits from the third collection of memory bits and comparing each bit in the second string of read bits with a corresponding bit in the third string of read bits.

4. The method of claim 3, further comprising determining that a fault has occurred in at least one of the second collection of memory bits and the third collection of memory bits when at least one of the second string of read bits differs from a corresponding read bit of the third string of read bits.

5. The method of claim 3, further comprising writing a string of bits to a fourth collection of memory bits, reading a fourth string of read bits from the fourth collection of memory bits and comparing each bit in the third string of read bits with a corresponding bit in the fourth string of read bits.

6. The method of claim 5, further comprising determining that a fault has occurred in at least one of the third collection of memory bits and the fourth collection of memory bits when at least one of the third string of read bits differs from a corresponding read bit of the fourth string of read bits.

7. The method of claim 1, wherein writing the string of bits to the first collection of memory bits and the second collection of memory bits comprises writing to the first collection of memory bits and to the second collection of memory bits separated by at least one other collection of memory bits.

8. The method of claim 1, wherein writing the string of bits comprises writing to the first collection of memory bits in a first memory bank and the second collection of memory bits in a second memory bank.

9. The method of claim 1, wherein writing a string of bits to a first collection of memory bits and a second collection of memory bits is performed in parallel.

10. The method of claim 1, wherein reading a first string of read bits from the first collection of memory bits, and reading a second string of read bits from the second collection of memory bits is performed in parallel.

11. The method of claim 1, wherein comparing each bit in the first string of read bits with a corresponding one in the second string of read bits is performed in parallel.

12. The method of claim 1, wherein writing, reading, and comparing are performed as part of a power up operation of a computer system.

13. The method of claim 1, wherein writing the string of bits comprises using a pattern of bits selected from the group consisting of pseudo-randomized and deterministic test patterns.

14. A method for dynamically testing and repairing a memory, comprising:

testing a plurality of memory segments to identify a faulty memory segment;

identifying an unmapped spare memory segment; and

remapping the spare memory segment to replace the faulty memory segment.

15. The method of claim 14, wherein remapping the spare memory segment comprises permanently remapping the spare memory segment by blowing an antifuse within a semiconductor device.

16. The method of claim 14, wherein remapping the spare memory segment comprises temporarily remapping the spare memory segment by asserting a gate of a MOSFET transistor.

17. The method of claim 14, wherein the testing is performed and controlled by an external source.

18. The method of claim 14, wherein the testing is performed and controlled by an internal built in test circuit.

19. The method of claim 14, wherein the testing, the identifying and remapping are performed as part of a power up operation of a computer system.

20. The method of claim 14, wherein testing, identifying and remapping are performed and controlled by a basic input output system of a processor.