Partial erase verify

• US 7,468,926 B2
• Filed: 01/19/2006
• Issued: 12/23/2008
• Est. Priority Date: 01/19/2005
• Status: Expired due to Fees

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Shappir, Assaf, Eisen, Shai
• Primary Examiner(s): Luu, Pho M.
• Application Number:
  US11/335,321
• Publication Number:
  US 20060158940A1
• Time in Patent Office: 1,069 Days
• Field of Search: 365/185.29, 365/185.24, 365/218, 365/200, 365/185.19
• US Class Current: 365/218
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.

Claims

1. A method for erasing memory cells in a memory array, the method comprising:

applying an erase pulse to bits of a cell ensemble of a memory cell array; and

designating the entire cell ensemble as erase verified once an erase verification operation on a subgroup of the cell ensemble being erased indicates a memory cell threshold voltage (Vt) of each cell in the subgroup has reached an erase verify (EV) voltage level.

2. The method according to claim 1, wherein the entire cell ensemble is verified as being erased only after the subgroup has been verified as being erased.

3. The method according to claim 1, wherein the subgroup is verified as being erased to a level lower than the target EV level, in order to insure that the entire cell ensemble has been erased, even though not all the cells have been verified as such.

4. The method according to claim 1, further comprising minimizing verification time overhead.

5. The method according to claim 1, wherein performing the erase verification operation is done after clustering said subgroup to a subset of word lines to reduce switching overhead.

6. The method according to claim 1, and further comprising increasing a set margin between a read level and the erase verify level.

7. The method according to claim 1, further comprising increasing a set margin between a read level and the erase verify and program verify levels.

8. The method according to claim 1, further comprising applying an erase pulse to a plurality of subgroups of said cell ensemble, but not performing erase verification operations on all of said subgroups.

9. The method according to claim 1, further comprising checking that a number of bits have passed a set level, and producing a high probability that the entire cell ensemble has been passed erase verification, even though only a subgroup of cells have been physically verified as passing erase verification.

10. The method according to claim 9, further including applying extra erase pulses after erase verification has been completed.

11. The method according to claim 9, where the subgroup of the cell ensemble which is erase verified is alternated between all the subgroups comprising the cell ensemble, regularly, periodically or randomly from erase operation to erase operation.