Method for dynamic insertion loss control for 10/100/1000 MHz Ethernet signaling

• US 7,469,348 B2
• Filed: 08/19/2005
• Issued: 12/23/2008
• Est. Priority Date: 03/28/2005
• Status: Active Grant

• Current Assignee: Kinetic Technologies International Holdings LP
• Original Assignee: Akros Silicon, Inc. (Kinetic Technologies Incorporated)
• Inventors: Camagna, John R., Crawley, Phillip John
• Primary Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US11/207,602
• Publication Number:
  US 20060238250A1
• Time in Patent Office: 1,222 Days
• Field of Search: 713/300
• US Class Current: 713/300
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence
• CPC Class Codes: H04L 12/10 Current supply arrangements

Abstract

Dynamic insertion insertion loss for an ethernet power on differential cable pairs is shown in a power feed circuit that supplies power to a network attached device (PD). An insertion loss control circuit limits power loss in a coupled power feed circuit. determines an insertion loss limit, and senses an average power of the power signals to produce a common mode feedback signal to the power feed circuit.

Claims

1. An insertion loss control limit circuit operable to supply an insertion loss limit to a coupled power feed circuit, the insertion loss control limit circuit comprising:

a first amplifier operably coupled to a pair of network power signals, wherein the amplifier is operable to generate a power estimate signal associated with the network power signals;

a rectifier operable to convert the power estimate signal into a single ended rectified power estimate; and

a loop filter operable to produce an insertion loss control limit, wherein the insertion loss control limit is based on the received pair of network power signals.

2. The insertion loss control limit circuit of claim 1, further comprising a buffer operable to prevent overloading of the loop filter.

3. The insertion loss control limit circuit of claim 1, wherein the loop filter stabilizes the insertion loss control circuit.

4. The insertion loss control limit circuit of claim 1 operable to reduce the insertion loss based on transmission losses.

5. A power feed circuit operable to supply power to an Ethernet network device coupled to an Ethernet network, comprising:

two differential transistor pairs wherein each transistor is operable to pass an Ethernet power signal;

two pairs of impedance sense resistors coupled to a transistor, wherein each impedance sense resistors is operable to pass a Ethernet power signals received from a drain of the coupled transistor;

an insertion loss control limit circuit operable to provide a insertion loss limit to a common mode feedback amplifier, wherein the common mode feedback amplifier senses an average Ethernet power signal and wherein the common mode feedback amplifier outputs a common mode feedback signal;

a differential amplifier coupled to the drains of each differential transistor pair, wherein the differential amplifier(s) are operable to;

receive the common mode feedback signal;

amplify a differential voltage across the pair of impedances coupled to the differential transistor pair; and

apply a feedback signal to a gate of the transistors of each differential transistor pair based on the differential voltage and common mode feedback signal, wherein the applied feedback signal;

drives the Ethernet power signal passed by each transistor in a differential transistor pair to be equal; and

reduces the insertion loss to the insertion loss limit; and

a pair of output nodes, wherein one output node is associated with each differential transistor pair, and wherein the pair of output nodes feed power to the Ethernet network device.

6. The power feed circuit of claim 5, wherein the power feed circuit is implemented as an integrated circuit (IC).

7. The power feed circuit of claim 5, wherein the power feed circuit interfaces to a switching/rectifying circuit operable to rectify an Ethernet power signal.

8. The power feed circuit of claim 7, wherein the switching/rectifying circuit interfaces with a plurality of twisted pairs, wherein the plurality of twisted pairs passes the Ethernet power signal, and wherein the insertion loss limit is determined by an Ethernet PHY based on an Ethernet communication signal.

9. The power feed circuit of claim 5, further comprising splitting circuitry operable to separate a data signal from the Ethernet power signal, and wherein the data signal is passed to an Ethernet PHY module.

10. The power feed circuit of claim 5, wherein the insertion loss control limit circuit couples to the received Ethernet power signals, and wherein the insertion loss limit is based on a differential RM.S root mean square (RMS) of the received Ethernet power signals.

11. The power feed circuit if claim 5, wherein the insertion loss control limit circuit further comprises:

a first amplifier operably coupled to a pair of Ethernet power signals, wherein the amplifier is operable to generate a power estimate signal associated with the Ethernet power signals;

a rectifier operable to convert the power estimate signal into a single ended power estimate; and

a loop filter operable to produce the insertion loss control signal, wherein a speed of the insertion loss control signal is based on the received pair of Ethernet power signals.

12. The power feed circuit if claim 11, wherein the insertion loss control circuit is operable to reduce the insertion loss based on transmission losses.

13. The power feed circuit of claim 5, wherein the average Ethernet power signal is sensed between a pair of common mode impedances across a source of the differential transistor pair.

14. The power feed circuit of claim 9, wherein the splitting circuitry comprises direct current (DC) blocking capacitors.

15. The power feed circuit of claim 6, wherein the integrated circuit (IC) further comprises:

an Ethernet physical layer (PHY) module;

an Ethernet media access controller (MAC) wherein the Ethernet PHY module and Ethernet MAC are operable to implement hardware layers of an Ethernet protocol stack;

a power management module; and

Ethernet network device specific processors and memory.

16. The power feed circuit of claim 5, operable to provide:

a high differential mode impedance across the pair of output nodes with the differential amplifier; and

a low common mode impedance across the pair of output nodes with the common mode amplifier.

17. A method to at least partially power an Ethernet network powered device, from an Ethernet power signal fed through an Ethernet network connection, comprising:

receiving a plurality of paired Ethernet power signals;

passing each pair of Ethernet power signal through a differential transistor pairs;

sensing a drain voltage at a drain of each transistor;

determining an insertion loss limit associated with the Ethernet power signals;

determining a common mode feedback signal based on the Ethernet power signals and insertion loss limit;

comparing the drain voltages of each differential transistor producing a pair of control signals for each differential transistor pair based on;

the comparison of the drain voltages of each differential transistor pair; and

the common mode feedback signal;

applying the control signal to a gate of each transistor, wherein the control signal;

equalizes the Ethernet power signal passed by each transistor in a differential transistor pair; and

limits the insertion loss associated with the Ethernet power signal; and

passing the Ethernet power signal from a pair of output nodes wherein one output node is associated with each differential transistor pair, and wherein the pair of output nodes feed power to the Ethernet network device.

18. The method of claim 17, wherein the insertion loss limit is based on a differential root mean square (RMS) of the received Ethernet power signals.

19. The method of claim 17, wherein the insertion loss limit is determined by an Ethernet PHY based on an Ethernet communication signal.

20. The method of claim 17, further comprising:

physically coupling the Ethernet network device to the Ethernet network;

receiving an Ethernet signal from the Ethernet network, wherein the Ethernet signal comprises the plurality of Ethernet power signals and/or communication signal(s); and

rectifying the Ethernet power signals.

21. The method of claim 17, wherein:

an RJ45 connector physically couples the Ethernet network device to the Ethernet network, and wherein the RJ45 connector couples to twisted pairs that further comprise conductors 1 and 2;

3 and 6;

4 and 5; and

7 and 8; and

a diode bridge network rectifies the Ethernet power signal received utilizing conductors 1, 2, 3, and 6 or conductors 4, 5, 7, and 8.