Wafer bonding method

• US 7,470,142 B2
• Filed: 03/29/2005
• Issued: 12/30/2008
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/092,498
• Publication Number:
  US 20050280042A1
• Time in Patent Office: 1,372 Days
• Field of Search: 438/455, 438/406, 438/118, 438/622, 438/623, 438/624, 257/782, 257/784
• US Class Current: 439/406
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29199 Material of the matrix
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29298 Fillers
• CPC Class Codes: H01L 2224/29299 Base material
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A method of coupling substrates together includes steps of providing first and second substrates. The second substrate includes a conductive bonding region positioned on its surface. Heat is provided to the conductive bonding region to reduce its number of defects. The surface of the conductive bonding region is bonded to the first substrate so that the conductive bonding region and the first substrate are coupled together.

Claims

1. A method of coupling substrates together comprising:

providing a first substrate;

providing a second substrate which carries a conductive bonding region;

providing a first amount of heat for a predetermined amount of time to the conductive bonding region to reduce its number of defects;

bonding a surface of the conductive bonding region to the first substrate so that the conductive bonding region and the first substrate are coupled together; and

processing the second substrate to form a vertically oriented semiconductor device.

2. The method of claim 1 wherein the step of providing the first amount of heat to the conductive bonding region includes providing visible light incident to the bonding surface to reflow its surface.

3. The method of claim 1 wherein the energy of the first amount of heat is chosen to increase the temperature of the conductive bonding region to reflow its surface.

4. The method of claim 1 wherein the step of bonding the surface of the conductive bonding region to the first substrate includes providing a second amount of heat to the conductive bonding region, where the energy of the second amount of heat is less than the energy of the first amount of heat.

5. The method of claim 1 wherein the second substrate includes electrical circuitry coupled to the conductive bonding region.

6. The method of claim 5 wherein the predetermined amount of time is chosen so that the temperature of the electrical circuitry is not increased above a predetermined temperature in response to the first amount of heat.

7. The method of claim 5 wherein the step of bonding the surface of the conductive bonding region to the first substrate includes providing a second amount of heat to the conductive bonding region, the second amount of heat being chosen so that the temperature of the electrical circuitry is not increased above a predetermined temperature which will decrease the performance of the electrical circuitry.

21. The method of claim 1 wherein the second substrate is processed to form the vertically oriented semiconductor device after the conductive bonding region and first substrate are coupled together.

22. The method of claim 1 further including processing the conductive bonding region to form a contact.

23. The method of claim 22 wherein the vertically oriented semiconductor device is carried by the contact.

24. The method of claim 22 wherein the first substrate includes a circuit which is in communication with the vertically oriented semiconductor device through the contact.

25. The method of claim 24 further including an interconnect extending between the circuit and contact, wherein the interconnect extends through a dielectric region.

8. A method of coupling substrates together comprising:

providing a first substrate which carries electrical circuitry;

providing a conductive line connected to the electrical circuitry and extending through an interlayer dielectric region carried by the first substrate;

providing a second substrate which carries a conductive bonding region;

providing a first amount of heat for a predetermined amount of time to the conductive bonding region; and

bonding the conductive bonding region to the interlayer dielectric region so the conductive bonding region is connected to the electrical circuitry through the conductive line.

9. The method of claim 8 further including removing a portion of the second substrate and forming a device therewith, the device being connected to the electrical circuitry through the conductive line.

10. The method of claim 8 wherein the energy of the first amount of heat is chosen to increase the temperature of the first conductive bonding region to reflow its surface.

11. The method of claim 8 wherein the step of bonding the conductive bonding region to the interlayer dielectric region includes providing a second amount of heat to the conductive bonding region, where the energy of the second amount of heat is less than the energy of the first amount of heat.

12. The method of claim 11 wherein the time the second amount of heat is provided is restricted so the temperature of the electrical circuitry is not increased above a predetermined temperature.

13. The method of claim 11 wherein the step of bonding the conductive bonding region to the interlayer dielectric region includes providing a second amount of heat to the conductive bonding region, the energy of the second amount of heat being chosen so the temperature of the electrical circuitry is not increased above a predetermined temperature.

26. The method of claim 8 further including processing the second substrate to form a vertically oriented semiconductor device.

27. The method of claim 26 further including processing the conductive bonding region to form a contact, wherein the contact is connected to the conductive line.

28. The method of claim 27 wherein the vertically oriented semiconductor device is carried by the contact.

29. The method of claim 26 wherein the vertically oriented semiconductor device operates as a memory device.

30. The method of claim 26 wherein the second substrate is processed to form the vertically oriented semiconductor device after the conductive bonding region and interlayer dielectric region are bonded together.

14. A method of coupling substrates together comprising:

providing a first substrate which carries electrical circuitry;

providing an interlayer dielectric region carried by the first substrate;

providing a conductive line connected to the electrical circuitry and extending through the interlayer dielectric region;

providing a second substrate which carries a conductive bonding region;

providing a first amount of heat for a first amount of time to the conductive bonding region;

providing a second amount of heat for a second amount of time to the conductive bonding region and bonding the conductive bonding region to the interlayer dielectric region; and

removing a portion of the second substrate.

15. The method of claim 14 wherein the conductive bonding region is connected to the electrical circuitry through the conductive line.

16. The method of claim 14 wherein the second amount of time is less than the first amount of time.

17. The method of claim 14 wherein the energy of the first amount of heat is chosen to increase the temperature of the conductive bonding region to reflow its surface.

18. The method of claim 14, wherein the energy of the second amount of heat is less than the energy of the first amount of heat.

19. The method of claim 14 wherein the time the second amount of heat is provided is restricted so the temperature of the electrical circuitry is not increased above a predetermined temperature.

20. The method of claim 14, further including processing the portion of the second substrate that is not removed to form a device connected to the electrical circuitry through the conductive line.

31. The method of claim 14 further including forming a vertically oriented semiconductor device by processing the portion of the second substrate that is not removed.

32. The method of claim 31 further including processing the conductive bonding region to form a contact.

33. The method of claim 32 wherein the vertically oriented semiconductor device is carried by the contact.

34. The method of claim 14 further including processing the second substrate and conductive bonding region to form a vertically oriented semiconductor device carried by a contact.

35. A method of coupling substrates together comprising:

providing a first substrate which carries electrical circuitry;

providing a conductive line and interlayer dielectric region carried by the first substrate, the conductive line being connected to the electrical circuitry and extending through the interlayer dielectric region;

providing a second substrate;

coupling the first and second substrates together by using a conductive bonding region; and

processing the second substrate to form a vertically oriented semiconductor device.

36. The method of claim 35 further including processing the conductive bonding region to form a contact.

37. The method of claim 36 wherein the vertically oriented semiconductor device is carried by the contact.

38. The method of claim 36 wherein the vertically oriented semiconductor device is in communication with the electrical circuitry through the contact and conductive line.

39. The method of claim 35 wherein the second substrate is processed to form the vertically oriented semiconductor device after the first and second substrates are coupled together.

40. The method of claim 35 wherein the contact couples the vertically oriented semiconductor device and conductive line together.

41. The method of claim 35 wherein the step of coupling the first and second substrates together includes forming a bonding interface between the vertically oriented semiconductor device and conductive line.

42. The method of claim 41, wherein the vertically oriented semiconductor device is formed after the bonding interface is formed.