Semiconductor layer structure and method of making the same

• US 7,470,598 B2
• Filed: 03/29/2005
• Issued: 12/30/2008
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Primary Examiner(s): Tran; Long K
• Application Number:
  US11/092,499
• Publication Number:
  US 20050282356A1
• Time in Patent Office: 1,372 Days
• Field of Search: 438/458, 438/455, 438/118, 438/622, 438/138, 438/152, 257/E27.011, 257/E27.02, 257/E27.088, 257/E27.122, 257/E21.388, 257/E21.703
• US Class Current: 438/455
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y10S 257/928 : with shorted PN or schottky junction other than emitter junction

Abstract

A method of forming a circuit includes providing a first substrate; positioning an interconnect region on a surface of the first substrate; providing a second substrate; positioning a device structure on a surface of the second substrate, the device structure including a stack of at least three doped semiconductor material layers; and bonding the device structure to the interconnect region.

Claims

1. A method of forming a circuit comprising:

providing a first substrate which carries electronic circuitry;

positioning an interconnect region on a surface of the first substrate;

providing a second substrate which carries a detach region and a device structure, the device structure including a stack of single crystalline semiconductor material layers, at least a portion of the device structure being doped;

bonding the device structure to the interconnect region;

removing at least a portion of the second substrate from the device structure by etching; and

processing the device structure to form at least one electronic device therewith;

wherein at least one layer in the stack is intrinsically doped;

wherein the stack includes a first layer of a first conductivity type positioned between second and third layers of opposite conductivity types, the doping concentration of the first layer near the second layer being different from the doping concentration of the first layer near the third layer.

2. A method of forming a circuit comprising:

providing a first substrate which carries electronic circuitry;

forming an interconnect region on a surface of the first substrate;

providing a second substrate which carries a detach region and a device structure, the device structure including a stack of doped semiconductor material layers, at least a portion of the device structure including single crystalline material;

wherein the stack of doped semiconductor material layers includes a layer with a graded doping concentration;

wherein a portion of the device structure is doped by the out-diffusion of impurity dopants from at least one of the second substrate and detach region;

coupling the device structure to the interconnect region;

removing at least a portion of the second substrate from the device structure by cleaving through the detach region; and

processing the device structure to form at least one electronic device therewith, the electronic device(s) being electrically coupled to the electronic circuitry through the interconnect region.

3. A method of forming a circuit comprising:

providing a first substrate which carries electronic circuitry;

forming an interconnect region on a surface of the first substrate;

providing a second substrate which carries a device structure, the device structure including a stack of doped semiconductor material layers, at least a portion of the device structure including single crystalline material;

wherein the stack of doped semiconductor material layers includes a layer with a graded doping concentration;

wherein a portion of the device structure is doped by the out-diffusion of impurity dopants from the detach region;

coupling the device structure to the interconnect region;

removing at least a portion of the second substrate from the device structure by cleaving through the detach region; and

processing the device structure to form at least one electronic device therewith, the electronic device(s) being electrically coupled to the electronic circuitry through the interconnect region.

4. A method of forming a circuit comprising:

providing a first substrate which carries electronic circuitry;

forming an interconnect region on a surface of the first substrate;

providing a second substrate which carries a detach region and a device structure, the device structure including a stack of doped semiconductor material layers, at least a portion of the device structure including single crystalline material;

wherein the stack of doped semiconductor material layers includes a first layer with a graded doping concentration;

wherein a portion of the device structure is doped by the out-diffusion of impurity dopants from the second substrate and/or detach region;

coupling the device structure to the interconnect region;

removing at least a portion of the second substrate from the device structure by cleaving through the detach region; and

processing the device structure to form at least one electronic device therewith, the electronic device(s) being electrically coupled to the electronic circuitry through the interconnect region.

5. The method of claim 4 wherein the stack includes at least one p-n junction.

6. The method of claim 4 wherein the stack includes alternately doped semiconductor layers.

7. The method of claim 4 wherein the detach region includes at least one of a dielectric material region, a hydrogen doped region, and a porous region.

8. The method of claim 4 wherein the detach region is formed after forming the device structure.

9. The method of claim 4 wherein the stack of semiconductor layers is formed by ion implantation.

10. The method of claim 4 wherein the doping concentration of at least one layer in the stack of semiconductor material layers is chosen to enhance the flow of minority carriers therethrough.

11. The method of claim 4 wherein at least one of the electronic device(s) is a vertically oriented semiconductor device.

12. The method of claim 4 wherein the stack of semiconductor material layers extends away from the interconnect region.

13. The method of claim 4 wherein the step of processing the device structure includes forming a dielectric region which extends around the stack of semiconductor material layers.

14. A method of forming a circuit comprising:

providing a first substrate which carries electronic circuitry;

forming an interconnect region which is connected to the electronic circuitry;

providing a second substrate which carries a device structure, the device structure including a stack of doped semiconductor material layers, at least a portion of the device structure including single crystalline material;

coupling the device structure to the interconnect region; and

processing the device structure to form a vertically oriented semiconductor device therewith, the vertically oriented semiconductor device being formed after the device structure is coupled to the interconnect region.

15. The method of claim 14 wherein the step of forming the vertically oriented semiconductor device includes etching the device structure to form a mesa structure.

16. The method of claim 15 wherein the step of forming the vertically oriented semiconductor device includes forming a dielectric material region around the mesa structure.

17. The method of claim 16 wherein the step of forming the vertically oriented semiconductor device includes forming a control terminal around the dielectric material region.

18. The method of claim 14 wherein the device structure and interconnect region are coupled together through a conductive region.

19. The method of claim 18 wherein the step of forming the vertically oriented semiconductor device includes etching the device structure to form a mesa structure, the mesa structure being carried by the conductive region.

20. The method of claim 14 wherein the device structure and interconnect region are coupled together through a conductive region.

21. The method of claim 20 wherein the mesa structure is carried by the conductive region.

22. A method of forming a circuit comprising:

providing a first substrate which carries electronic circuitry;

forming an interconnect region;

providing a second substrate which carries a device structure, the device structure including a stack of doped semiconductor material layers, at least a portion of the device structure including single crystalline material;

coupling the device structure to the interconnect region; and

processing the device structure to form a vertically oriented semiconductor device therewith;

wherein the vertically oriented semiconductor device is formed after the device structure is coupled to the interconnect region;

wherein the step of forming the vertically oriented semiconductor device includes etching the device structure to form a mesa structure.

23. The method of claim 22 wherein the stack of doped semiconductor material layers includes a layer with a graded doping concentration.

24. The method of claim 22 wherein a portion of the device structure is doped by the out-diffusion of impurity dopants.

25. The method of claim 22 wherein the step of forming the vertically oriented semiconductor device includes forming a dielectric material region around the mesa structure, and forming a control terminal around the dielectric material region.