Memory cell array structures in NAND flash memory devices

• US 7,470,948 B2
• Filed: 12/28/2006
• Issued: 12/30/2008
• Est. Priority Date: 03/07/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jung-Dal, Park, Ki-Tae
• Primary Examiner(s): Dang; Phuc T
• Application Number:
  US11/617,233
• Publication Number:
  US 20070210372A1
• Time in Patent Office: 733 Days
• Field of Search: 257/314, 257/315, 257/318, 257/319, 438/247, 438/258
• US Class Current: 257/314
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A NAND-type non-volatile semiconductor memory device includes a gate insulating layer on an active region of a semiconductor substrate, first and second select gate structures on the active region, and a memory gate structure therebetween. The first and second select gate structures respectively include a plurality of select gate patterns, and the memory gate structure includes a plurality of storage gate patterns. The gate insulating layer includes a plurality of openings therein exposing portions of the active region between ones of the plurality of select gate patterns of the first and second select gate structures. The device may further include impurity regions in portions of the active region between the gate patterns, and halo regions adjacent ones of the impurity regions in the portions of the active region exposed by the openings in the gate insulating layer. Related fabrication methods are also discussed.

Claims

1. A cell array structure of a NAND flash memory, comprising:

a semiconductor substrate including an active region therein and having an inner region and an outer region;

a memory gate structure including a plurality of word lines crossing over the active region, the memory gate structure being disposed on the inner region;

a select gate structure crossing over the active region, wherein the select gate structure comprises a plurality of string selection lines and a plurality of ground selection lines respectively disposed on opposite sides of the memory gate structure, respectively; and

impurity regions disposed in the active region between the plurality of word lines, between the plurality of string selection lines, between the plurality of ground selection lines, between one of the plurality of string selection lines and an immediately adjacent one of the plurality of word lines, and between one of the plurality of ground selection lines and an immediately adjacent one of the plurality of word lines,

wherein the impurity regions in the inner region have different impurity concentration distributions than the impurity regions in the outer region, and wherein one of the plurality of string selection lines and one of the plurality of ground selection lines are disposed on respective interfaces between the inner region and the outer region on the opposite sides of the memory gate structure.

2. The cell array structure of the NAND flash memory of claim 1, further comprising a charge-storing pattern disposed under the memory and select gate structures to cover a predetermined region of the active region,

wherein the charge-storing pattern covers surfaces of the active region between ones of the plurality of word lines of the inner region, but exposes portions of the active region between ones of the plurality of string selection lines and portions of the active region between ones of the plurality of ground selection lines of the outer region.

3. The cell array structure of the NAND flash memory of claim 2, wherein the charge-storing pattern is formed of at least one selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

4. The cell array structure of the NAND flash memory of claim 2, further comprising outer halo regions disposed adjacent lower portions of the impurity regions of the outer region,

wherein the outer halo regions are formed in the portions of the active region exposed by the charge-storing pattern.

5. The cell array structure of the NAND flash memory of claim 4, wherein the impurity regions have a different conductivity type from the semiconductor substrate, and wherein the outer halo regions have a same conductivity type as the semiconductor substrate.

6. The cell array structure of the NAND flash memory of claim 4, further comprising inner halo regions disposed around lower portions of the impurity regions of the inner region,

wherein the inner halo regions have a same conductivity type as the outer halo regions and have lower impurity concentrations than the outer halo regions.

7. The cell array structure of the NAND flash memory of claim 4, wherein the outer halo regions are locally formed in the outer region so that the active regions at either side of each of the string and ground selection lines disposed on the interface between the inner region and the outer region have asymmetric impurity concentration distributions.

8. The cell array structure of the NAND flash memory of claim 1, wherein the string selection lines comprise:

an outer string selection line disposed at one side of the memory gate structure; and

an inner string selection line disposed between the outer string selection line and the memory gate structure,

wherein the ground selection lines comprise;

an outer ground selection line disposed at the other side of the memory gate structure; and

an inner ground selection line disposed between the outer ground selection line and the memory gate structure,

and wherein the inner string selection line and the inner ground selection line are disposed on the interface between the inner region and the outer region, and wherein linewidths of the inner string selection line and inner ground selection line are greater than or equal to that of one of the plurality of word lines.

9. The cell array structure of the NAND flash memory of claim 8, further comprising:

at least one intermediate string selection line disposed between the inner and outer string selection lines; and

at least one intermediate ground selection line disposed between the inner and outer ground selection lines.

10. The cell array structure of the NAND flash memory of claim 1, wherein spaces between ones of the plurality of string selection lines, between ones of the plurality of ground selection lines, between one of the plurality of string selection lines and an immediately adjacent one of the plurality of word lines, and between one of the plurality of ground selection lines and an immediately adjacent one of the plurality of word lines, are greater than or substantially equal to a distance between ones of the plurality of word lines.

11. The cell array structure of the NAND flash memory of claim 1, further comprising:

drain and source regions formed in the active region at one side and the other side of the memory gate structure, respectively;

bit lines crossing over the word lines and connected to each of the drain regions; and

a common source line crossing over the active region and connecting the source regions,

wherein the plurality of string selection lines are disposed between the drain region and the memory gate structure, and wherein the plurality of ground selection lines are disposed between the source region and the memory gate structure.

12. The cell array structure of the NAND flash memory of claim 1, wherein each of the plurality of word lines, the plurality of string selection lines and the plurality of ground selection lines comprises:

a lower gate electrode disposed on the active region; and

an upper gate electrode disposed on the lower gate electrode to cross over the active region,

wherein the plurality of word lines further comprise a gate interlayer insulating pattern disposed between the upper and lower gate electrodes to electrically isolate the lower and upper gate electrodes from each other.

13. The cell array structure of the NAND flash memory of claim 12, further comprising a gate insulating pattern disposed under the memory and select gate structures to cover a predetermined region of the active region,

wherein the gate insulating pattern is on surfaces of the active region between adjacent ones of the plurality of word lines on the inner region of the inner region, but exposes portions of the active region between adjacent ones of the plurality of string selection lines and adjacent ones of the plurality of ground selection lines on the outer region.

40. The cell array structure of the NAND flash memory of claim 12, wherein the plurality of string selection lines and the plurality of ground selection lines do not comprise the gate interlayer insulating pattern between the upper and lower gate electrodes.

41. The cell array structure of the NAND flash memory of claim 1, wherein portions of the active region at either side of each of the plurality of word lines have substantially similar impurity concentration distributions regardless of a position of one of the plurality of word lines.

42. The cell array structure of the NAND flash memory of claim 1, wherein two impurity regions, which are adjacent to the string selection line or the ground selection line that are disposed on an interface between the inner region and the outer region, are asymmetric.

14. A cell array structure of a NAND flash memory comprising:

a semiconductor substrate including an active region therein and having an inner region and an outer region;

a plurality of gates disposed on the inner region and the outer region of the substrate to cross over the active region;

impurity regions in the active region between the plurality of gates;

a gate insulating pattern disposed between the plurality of gates and the semiconductor substrate, wherein the gate insulating pattern is on surfaces of the active region between adjacent ones of the plurality of gates on the inner region and has openings exposing portions of the active region between adjacent ones of the plurality of gates on the outer region; and

outer halo regions in the active region adjacent lower portions of ones of the impurity regions of the outer region.

15. The cell array structure of the NAND flash memory of claim 14, wherein the outer halo regions are locally formed only in the outer region and not in the inner region.

16. The cell array structure of the NAND flash memory of claim 14, further comprising inner halo regions formed around lower portions of the impurity regions of the inner region,

wherein the inner halo regions have a same conductivity type as the outer halo region and have a lower impurity concentration than the outer halo regions.

17. The cell array structure of the NAND flash memory of claim 14, wherein the outer halo regions are locally formed adjacent the ones of the impurity regions in the portions of the active region exposed by the openings.

18. The cell array structure of the NAND flash memory of claim 14, wherein the gate insulating pattern is formed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer which are stacked in sequence.

19. The cell array structure of the NAND flash memory of claim 14, wherein the plurality of gates comprise:

a plurality of word lines disposed in the inner region; and

a plurality of string selection lines and a plurality of ground selection lines disposed at one side and the other side of the plurality of word lines,

wherein ones of the pluralities of string and ground selection lines immediately adjacent to the plurality of word lines are disposed on the interface between the inner region and the outer region.

20. The cell array structure of the NAND flash memory of claim 19, wherein the string selection lines comprises:

an outer string selection line disposed at one side of the plurality of word lines; and

an inner string selection line disposed between the outer string selection line and one of the plurality of word lines adjacent thereto,

wherein the ground selection lines comprises;

an outer ground selection line disposed at the other side of the plurality of word lines; and

an inner ground selection line disposed between the outer ground selection line and one of the plurality of word lines adjacent thereto,

and wherein the inner string selection line and the inner ground selection line are disposed on the interface between the inner region and the outer region, and linewidths of the inner string selection line and inner ground selection line are equal to or greater than that of one of the word lines.

21. The cell array structure of the NAND flash memory of claim 20, further comprising:

at least one intermediate string selection line disposed between the inner and outer string selection lines; and

at least one intermediate ground selection line disposed between the inner and outer ground selection lines.

22. The cell array structure of the NAND flash memory of claim 19, wherein spaces between the plurality of string selection lines, between the plurality of ground selection lines, between the string selection line and an adjacent word line, and between the ground selection line and an adjacent word line, are substantially equal to or greater than a distance between the plurality of word lines.

23. The cell array structure of the NAND flash memory of claim 19, wherein the outer halo regions are locally formed in the outer region so that the portions of the active region at either side of each of the pluralities of string and ground selection lines disposed on the interface between the inner region and the outer region have asymmetric impurity concentration distributions.

24. The cell array structure of the NAND flash memory of claim 19, wherein each of the plurality of word lines, the plurality of string selection lines and the plurality of ground selection lines comprises:

a lower gate electrode disposed on the active region; and

an upper gate electrode disposed on the lower gate electrode to cross over the active region,

wherein the plurality of word tines further comprise a gate interlayer insulating pattern disposed between the upper and lower gate electrodes to electrically isolate the lower and upper gate electrodes, which are respectively used as a floating gate electrode and a control gate electrode.

25. The cell array structure of the NAND flash memory of claim 14, further comprising:

drain and source regions formed on the active region at one side and the other side of the plurality of gates, respectively;

bit lines crossing over the plurality of gates and connected to each of the drain regions; and

a common source line crossing over the active region and connecting the source regions.

26. A NAND-type non-volatile semiconductor memory device, comprising:

a semiconductor substrate including an active region therein;

a gate insulating layer on the active region of the substrate;

first and second select gate structures respectively comprising a plurality of select gate patterns on the active region of the substrate; and

a memory gate structure comprising a plurality of storage gate patterns on the active region of the substrate between the first and second select gate structures,

wherein the gate insulating layer is on portions of the active region between adjacent ones of the plurality of storage gate patterns of the memory gate structure and includes a plurality of openings therein exposing portions of the active region between adjacent ones of the plurality of select gate patterns of the first and second select gate structures.

27. The device of claim 26, further comprising:

a plurality of impurity regions in portions of the active region between ones of the plurality of storage gate patterns of the memory gate structure, between the ones of the plurality of select gate patterns of the first and second select gate structures, and between the memory gate structure and the first and second select gate structures; and

a plurality of halo regions adjacent ones of the plurality of impurity regions in the portions of the active region exposed by the openings in the gate insulating layer between the ones of the plurality of select gate patterns of the first and second select gate structures.

28. The device of claim 27, wherein the plurality of halo regions are adjacent opposing sides of the ones of the impurity regions in the portions of the active region exposed by the openings in the gate insulating layer.

29. The device of claim 27, wherein the plurality of halo regions comprise a plurality of outer halo regions, and further comprising:

a plurality of inner halo regions adjacent ones of the plurality of impurity regions in the portions of the active region between the ones of the plurality of storage gate patterns, between the first select gate structure and the memory gate structure, and between the second select structure and the memory gate structure,

wherein the plurality of outer halo regions have a greater impurity concentration than the plurality of inner halo regions.

30. The device of claim 27, wherein the plurality of halo regions have a same conductivity type as the semiconductor substrate and an opposite conductivity type as the plurality of impurity regions.

31. The device of claim 26, wherein portions of the active region immediately adjacent to outermost ones of the plurality of storage gate patterns on opposite sides thereof have substantially similar impurity concentration distributions.

32. The device of claim 26, wherein the first and second select gate structures respectively comprise an outer select gate pattern and an inner select gate pattern immediately adjacent to an outermost one of the plurality of storage gate patterns.

33. The device of claim 32, wherein portions of the active region immediately adjacent to the inner select gate pattern on opposing sides thereof have asymmetric impurity concentration distributions.

34. The device of claim 32, wherein the first and/or second select gate structures further comprise:

at least one intermediate select gate pattern between the outer select gate pattern and the inner select gate pattern.

35. The device of claim 32, wherein the inner select gate pattern has a width that is greater than or substantially equal to a width of one of the plurality of storage gate patterns, and wherein the outer select gate pattern has a width that is greater than the width of the one of the plurality of storage gate patterns.

36. The device of claim 32, wherein a distance between the outer select gate pattern and the inner select gate pattern is greater than a distance between the inner select gate pattern and the outermost one of the plurality of storage gate patterns.

37. The device of claim 36, wherein the distance between the inner select gate pattern and the outermost one of the plurality of storage gate patterns is substantially equal to a distance between ones of the plurality of storage gate patterns.

38. The device of claim 26, wherein the device comprises a charge-trapping type flash memory device, and wherein the gate insulating layer comprises a nitride layer.

39. The device of claim 26, wherein the device comprises a floating gate type flash memory device, wherein the plurality of storage gate patterns respectively comprise a floating gate pattern on the substrate and a control gate pattern on the floating gate pattern, and wherein the gate insulating layer comprises an oxide layer.