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Chip structure and process for forming the same

  • US 7,470,988 B2
  • Filed: 11/24/2004
  • Issued: 12/30/2008
  • Est. Priority Date: 12/21/1998
  • Status: Expired due to Fees
First Claim
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1. A chip comprising:

  • a silicon substrate;

    a transistor in or on said silicon substrate;

    a first copper layer over said silicon substrate;

    a second copper layer over said silicon substrate;

    a dielectric layer between said first and second copper layers;

    a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

    a contact pad over said silicon substrate, wherein said contact pad has a first top surface with a first region and a second region surrounding said first region;

    a passivation layer over said silicon substrate, over said first and second copper layers and on said second region, wherein a first opening in said passivation layer is over said first region and said first region is at a bottom of said first opening, wherein said first opening has a first width between 0.5 and 20 micrometers, and wherein said passivation layer has a second top surface with a third region surrounding said first opening and a fourth region surrounding said third region;

    a first polymer layer on said fourth region, wherein said first polymer layer has a thickness between 1 and 100 micrometers and greater than that of said passivation layer and that of said dielectric layer, and wherein a second opening in said first polymer layer is over said first opening, over said first region and over said third region, and said third region is at a bottom of said second opening, wherein said second opening has a second width greater than said first width; and

    an interconnecting structure on said first polymer layer, on said third region and on said first region, wherein said interconnecting structure is connected to said contact pad through said first and second openings, wherein said interconnecting structure comprises an electroplated metal, and wherein said interconnecting structure comprises a metal trace having a thickness greater than that of said first copper layer and that of said second copper layer.

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