Chip structure and process for forming the same

• US 7,470,988 B2
• Filed: 11/24/2004
• Issued: 12/30/2008
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Zarneke; David A
• Application Number:
  US10/997,145
• Publication Number:
  US 20050087844A1
• Time in Patent Office: 1,497 Days
• Field of Search: 257/759
• US Class Current: 257/759
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0251 : for MOS devices
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a contact pad over said silicon substrate, wherein said contact pad has a first top surface with a first region and a second region surrounding said first region;

a passivation layer over said silicon substrate, over said first and second copper layers and on said second region, wherein a first opening in said passivation layer is over said first region and said first region is at a bottom of said first opening, wherein said first opening has a first width between 0.5 and 20 micrometers, and wherein said passivation layer has a second top surface with a third region surrounding said first opening and a fourth region surrounding said third region;

a first polymer layer on said fourth region, wherein said first polymer layer has a thickness between 1 and 100 micrometers and greater than that of said passivation layer and that of said dielectric layer, and wherein a second opening in said first polymer layer is over said first opening, over said first region and over said third region, and said third region is at a bottom of said second opening, wherein said second opening has a second width greater than said first width; and

an interconnecting structure on said first polymer layer, on said third region and on said first region, wherein said interconnecting structure is connected to said contact pad through said first and second openings, wherein said interconnecting structure comprises an electroplated metal, and wherein said interconnecting structure comprises a metal trace having a thickness greater than that of said first copper layer and that of said second copper layer.

2. The chip of claim 1, wherein said passivation layer comprises a topmost inorganic insulating layer of said chip.

3. The chip of claim 1, wherein said first polymer layer comprises polyimide.

4. The chip of claim 1, wherein said passivation layer comprises silicon nitride.

5. The chip of claim 1, wherein said passivation layer comprises silicon oxide.

6. The chip of claim 1, wherein said electroplated metal comprises electroplated copper.

7. The chip of claim 1, wherein said electroplated metal comprises electroplated gold.

8. The chip of claim 1, wherein said electroplated metal comprises electroplated nickel.

9. The chip of claim 8 farther comprising a second polymer layer on said interconnecting structure.

10. The chip of claim 6, wherein a third opening in said second polymer layer is over a contact point of said interconnecting structure, and said contact point is at a bottom of said third opening, wherein said contact point is connected to said contact pad through said first and second openings.

11. The chip of claim 10, wherein the position of said contact point from a top perspective view is different from that of said contact pad.

27. The chip of claim 1, wherein said interconnecting structure further comprises a titanium-containing layer under said electroplated metal.

12. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a contact pad over said silicon substrate, wherein said contact pad has a top surface with a first region and a second region surrounding said first region;

a passivation layer over said silicon substrate, over said first and second copper layers and on said second region, wherein a first opening in said passivation layer is over said first region and said first region is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 1 and 100 micrometers and greater than that of said passivation layer and that of said dielectric layer, and wherein a second opening in said first polymer layer is over said first region; and

a metallization structure over said first polymer layer, wherein said metallization structure is connected to said contact pad through said second opening, and wherein said metallization structure comprises an electroplated metal.

13. The chip of claim 12, wherein said metallization structure is further on said contact pad and in said second opening.

14. The chip of claim 12, wherein said metallization structure is directly on said first polymer layer.

15. The chip of claim 12, further comprising a second polymer layer on said metallization structure.

16. The chip of claim 15, wherein a third opening in said second polymer layer is over a contact point of said metallization structure, and said contact point is at a bottom of said third opening, wherein said contact point is connected to said contact pad through said second opening.

17. The chip of claim 16, wherein the position of said contact point from a top perspective view is different from that of said contact pad.

18. The chip of claim 12, wherein said electroplated metal comprises electroplated copper.

19. The chip of claim 12, wherein said electroplated metal comprises electroplated gold.

20. The chip of claim 12, wherein said electroplated metal comprises electroplated nickel.

21. The chip of claim 12, wherein said passivation layer comprises a topmost inorganic insulating layer of said chip.

22. The chip of claim 12, wherein said first polymer layer comprises polyimide.

23. The chip of claim 12, wherein said passivation layer comprises silicon nitride.

24. The chip of claim 12, wherein said passivation layer comprises silicon oxide.

25. The chip of claim 12, wherein said metallization structure further comprises a titanium-containing layer under said electroplated metal.

26. The chip of claim 12, further comprising a bump connected with said metallization structure.