Amplifier shared between two columns in CMOS sensor

• US 7,471,324 B2
• Filed: 08/28/2002
• Issued: 12/30/2008
• Est. Priority Date: 08/28/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Krymski, Alexander, Tu, Nick
• Primary Examiner(s): Ye; Lin
• Assistant Examiner(s): Yoder, III; Chriss S
• Application Number:
  US10/229,176
• Publication Number:
  US 20040041931A1
• Time in Patent Office: 2,316 Days
• Field of Search: 348/294, 348/300, 348/301, 348/302, 348/303, 348/308, 348/332, 250/208.1
• US Class Current: 348/300
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 3/1568 for disturbance correction or prevention within the image-sensor, e.g. biasing, blooming, smearing correction circuits H04N25/62

Abstract

The present invention provides an improved shared amplifier circuitry and method of operation which minimizes offset and column to column fixed pattern noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the pixel array and increases the dynamic range of the pixel output and saves chip area. This is accomplished by simultaneously sampling and storing charge accumulated signals from a first and a second desired pixel from a respective first and second column. The circuit amplifies the first charge signal and then samples and amplifies the reset signal of the first desired pixel and subsequently outputs the amplified first charge signal and the reset signal. Then the circuit amplifies the second charge signal and the reset signal of the first desired pixel and subsequently outputs the amplified second charge signal and the reset signal.

Claims

1. A method of operating a shared column amplifier in an imaging pixel array, said method comprising:

sampling and holding a first charge accumulated signal from a first desired pixel in a first pixel array column;

sampling and holding a second charge accumulated signal from a second desired pixel in a second pixel array column;

sampling and holding at least one of a first and second respective reset signal from said first and second desired pixels;

sequentially amplifying through one amplifier circuit path said first sampled and held charge accumulated signal and then one of said sampled and held first and second reset signals;

providing, substantially simultaneously, said amplified signals of said first sampled and held charge accumulated signal and said one of said sampled and held first and second reset signals to a downstream circuit;

sequentially amplifying through said one amplifier circuit path said second sampled and held charge accumulated signal and then said one of said sampled and held first and second reset signals; and

providing, substantially simultaneously, said amplified signals of said second sampled and held charge accumulated signal and said one of said sampled and held first and second reset signals to a downstream circuit.

2. The method of claim 1, wherein said sampling and holding of said first and second charge accumulated signals is substantially simultaneous.

3. The method of claim 1, further comprising:

storing said amplified first and second charge accumulated signals.

4. The method of claim 1, further comprising:

storing said amplified at least one of said first and second reset signals.

5. The method of claim 4, wherein first and second reset signals are sampled and held and amplified by said amplifier, said method further comprising storing said amplified first and second reset signals.

6. The method of claim 1 further comprising:

buffering through a buffer said sampled and held first and second charge accumulated signals and said sampled and held at least one of said first and second reset signals.

7. The method of claim 1, wherein first and second reset signals are sampled and held and both said first and second reset signals are amplified by said one amplifier.

8. The method of claim 7, wherein said sampling and holding of said first and second reset signals is substantially simultaneous.

9. The method of claim 1, further comprising the step of:

sequentially storing, after said step of first sequentially amplifying and before said step of providing said amplified signals, said first sampled and held charge accumulated signal and said one of said sampled and held first and second reset signals in respective storage areas.

10. The method of claim 9, further comprising the step of:

sequentially storing, after said step of second sequentially amplifying and before said step of providing said amplified signals, said second sampled and held charge accumulated signal and said one of said sampled and held first and second reset signals in respective storage areas.

11. A shared column amplifier circuit for an imager, comprising:

a first circuit for sampling and holding an image signal from a first desired pixel in a first column of a pixel array;

a second circuit for sampling and holding an image signal from a second desired pixel in a second column of a pixel array;

at least one of said first and second circuits for further sampling and holding at least one reset signal from one of said first desired pixel and said second desired pixel; and

an amplifier circuit path for sequentially amplifying said sampled and held image signal from said first desired pixel and one of said at least one sampled and held reset signal and for sequentially amplifying said sampled and held image signal from said second desired pixel and said one of said at least one sampled and held reset signal.

12. The circuit of claim 11, wherein said amplifier circuit path is respectively switchably coupled to said first and second circuits.

13. The circuit of claim 11, wherein said first circuit further comprises:

a first storage circuit for said holding of said sampled image signal from said first desired pixel and a sampled associated reset signal.

14. The circuit of claim 13, wherein said second circuit further comprises:

a second storage circuit for said holding of said sampled image signal from said second desired pixel.

15. The circuit of claim 14, wherein said second storage circuit further comprises a first and a second storage areas.

16. The circuit of claim 15, wherein said first and second storage areas are capacitors.

17. The circuit of claim 14, wherein said second storage circuit is switchably coupled to said second desired pixel.

18. The circuit of claim 13, wherein said first storage circuit further comprises a first and second storage areas.

19. The circuit of claim 18, wherein said first and second storage areas are capacitors.

20. The circuit of claim 13, wherein said first storage circuit is switchably coupled to said first desired pixel.

21. The circuit of claim 13, wherein said second circuit further comprises:

a second storage circuit for said holding of said sampled image signal from said second desired pixel and a sampled associated reset signal.

22. The circuit of claim 11, further comprising:

a third storage circuit for storing said amplified signals.

23. The circuit of claim 22, wherein said third storage circuit is switchably coupled to a downstream circuit.

24. The circuit of claim 23, wherein said third storage circuit further comprises a first and second storage area, said first and second storage areas being respectively switchably coupled to said amplifier, said first and second storage areas being respectively switchably coupled to said downstream circuit.

25. The circuit of claim 24, wherein said first and second storage areas are capacitors.

26. The circuit of claim 11, further comprising:

a buffer for buffering said image and reset signals, said buffer respectively switchably coupled to said first and said second circuits, said buffer coupled to said amplifier.

27. A CMOS imager, comprising:

a CMOS pixel array including a first and second desired pixel; and

a shared column amplifier circuit, comprising;

first circuit for sampling and holding an image signal from said first desired pixel in a first column of said pixel array;

a second circuit for sampling and holding an image signal from said second desired pixel in a second column of said pixel array;

at least one of said first and second circuits further sampling and holding an associated reset signal from one of said first pixel and said second pixel;

an amplifier circuit path for sequentially amplifying said sampled and held image signal from said first desired pixel and one of said at least one associated reset signal and for sequentially amplifying said sampled and held image signal from said second desired pixel and said one of said at least one associated sampled and held reset signal.

28. The imager of claim 27, wherein said amplifier circuit path is respectively switchably coupled to said first and second circuits.

29. The imager of claim 27, wherein said first circuit further comprises:

a first storage circuit for said holding of said sampled image signal from said first desired pixel and said sampled associated reset signal.

30. The imager of claim 29, wherein said second circuit further comprises:

a second storage circuit for said holding of said sampled image signal from said second desired pixel.

31. The imager of claim 30, wherein said second storage circuit further comprises a first and a second storage areas.

32. The imager of claim 31, wherein said first and second storage areas are capacitors.

33. The imager of claim 30, wherein said second storage circuit is switchably coupled to said second desired pixel.

34. The imager of claim 29, wherein said first storage circuit further comprises a first and a second storage areas.

35. The imager of claim 34, wherein said first and second storage areas are capacitors.

36. The imager of claim 29, wherein said first storage circuit is switchably coupled to said first desired pixel.

37. The imager of claim 29, wherein said second circuit further comprises:

a second storage circuit for said holding of said sampled image signal from said second desired pixel and a sampled associated reset signal.

38. The imager of claim 27, further comprising:

a third storage circuit for storing said amplified signals.

39. The imager of claim 38, wherein said third storage circuit is switchably coupled to a downstream circuit.

40. The imager of claim 39, wherein said third storage circuit further comprises a first and second storage area, said first and second storage areas being respectively switchably coupled to said amplifier, said first and second storage areas being respectively switchably coupled to said downstream circuit.

41. The imager of claim 40, wherein said first and second storage areas are capacitors.

42. The imager of claim 27, further comprising:

a buffer for buffering said image and reset signals, said buffer respectively switchably coupled to said first and said second circuits, said buffer coupled to said amplifier.

43. A CMOS imager, comprising:

a CMOS pixel array including a first and second desired pixel; and

a shared column amplifier circuit, comprising;

a first circuit for sampling and holding an image signal from said first desired pixel in a first column of said pixel array;

a second circuit for sampling and holding an image signal from said second desired pixel in a second column of said pixel array;

at least one of said first and second circuits further sampling and holding an associated reset signal;

an amplifier circuit path for sequentially amplifying said image signals and said sampled and held reset signal; and

a third circuit for storing said amplified signals as first and second signal pairs in storage areas, said first signal pair including an amplified image signal from said first desired pixel and an amplified reset signal, and said second signal pair including an amplified image signal from said second desired pixel and said amplified reset signal.

44. The imager of claim 43, wherein said amplifier circuit path is respectively switchably coupled to said first and second circuits.

45. The imager of claim 43, wherein said first circuit further comprises:

a first storage circuit for said holding of said sampled image signal from said first desired pixel and said sampled associated reset signal.

46. The imager of claim 45, wherein said first storage circuit further comprises a first and a second storage areas.

47. The imager of claim 46, wherein said first and second storage areas are capacitors.

48. The imager of claim 45, wherein said first storage circuit is switchably coupled to said first desired pixel.

49. The imager of claim 43, wherein said second circuit further comprises:

a second storage circuit for said holding of said sampled image signal from said second desired pixel.

50. The imager of claim 49, wherein said second storage circuit further comprises a first and second storage areas.

51. The imager of claim 50, wherein said first and second storage areas are capacitors.

52. The imager of claim 49, wherein said second storage circuit is switchably coupled to said second desired pixel.

53. The imager of claim 43, wherein said third storage circuit is switchably coupled to a downstream circuit.

54. The imager of claim 43, wherein said storage areas of said third storage circuit comprises a first and second storage area, said first and second storage areas being respectively switchably coupled to said amplifier, said first and second storage areas being respectively switchably coupled to said downstream circuit.

55. The imager of claim 54, wherein said first and second storage areas are capacitors.

56. The imager of claim 43, further comprising:

a buffer for buffering said image and reset signals, said buffer respectively switchably coupled to said first and said second circuits, said buffer coupled to said amplifier.

57. The imager of claim 43, wherein said third circuit stores the same reset signal in each signal pair.

58. The imager of claim 43, wherein said third circuit stores different reset signals in each signal pair.

59. A method of operating a shared column amplifier in an imaging pixel array, said method comprising:

sampling and holding a first image signal from a first desired pixel in a first pixel array column;

sampling and holding a second image signal from a second desired pixel in a second pixel array column,

sampling and holding at least one of a first and second respective reset signal from said first and second desired pixels;

sequentially amplifying through one amplifier circuit path said first and second image signals and said at least one of said first and second reset signal;

storing said amplified signals as first and second signal pairs in respective first and second storage areas;

said first signal pair including an amplified first image signal from said first desired pixel and an amplified reset signal, and said second signal pair including an amplified second image signal from said second desired pixel and said amplified reset signal; and

providing said stored amplified signal pairs to a downstream circuit.

60. The method of claim 59, wherein said sampling and holding of at least one of a first and second respective reset signal comprises sampling and holding one reset signal from one of said first and second desired pixels;

said amplifying step comprises amplifying said one reset signal; and

said storing step comprises storing as said first signal pair an amplified first image signal from said first desired pixel and said amplified one reset signal and storing as said second signal pair an amplified second image signal from said second desired pixel and said amplified one reset signal.

61. The method of claim 59, wherein said sampling and holding of at least one of a first and second respective reset signal comprises sampling and holding a reset signal associated with each of said first and second desired pixels;

said amplifying step comprises amplifying said sampled and held reset signals associated with each of said first and second desired pixels; and

said storing step comprises storing as said first signal pair an amplified first image signal from said first desired pixel and said amplified reset signal from said first desired pixel and storing as said second signal pair an amplified second image signal from said second desired pixel and said amplified reset signal from said second desired pixel.

62. A method of operating a shared column amplifier in an imaging pixel array, said method comprising:

sampling and holding a first charge accumulated signal from a first desired pixel in a first pixel array column;

sampling and holding a second charge accumulated signal from a second desired pixel in a second pixel array column;

sampling and holding a first reset signal from one of said first desired pixel and second desired pixel;

amplifying through a first amplifier circuit path said first sampled and held charge accumulated signal;

amplifying through said first amplifier circuit path said first sampled and held reset signal;

amplifying through said first amplifier circuit path said second sampled and held charge accumulated signal;

amplifying through said first amplifier circuit path said first sampled and held reset signal;

providing said amplified first and second sampled and held charge accumulated signals to a downstream circuit;

sampling and holding a third charge accumulated signal from a third desired pixel in a third pixel array column;

sampling and holding a fourth charge accumulated signal from a fourth desired pixel in a fourth pixel array column;

amplifying through a second amplifier circuit path said third sampled and held charge accumulated signal;

amplifying through said second amplifier circuit path said fourth sampled and held charge accumulated signal; and

providing said amplified third and fourth sampled and held charge accumulated signals to said downstream circuit.

63. The method of claim 62, further comprising:

sampling and holding a second reset signal from said third desired pixel in said third pixel array column;

amplifying through said second amplifier circuit path said second sampled and held reset signal after said step of amplifying through a second amplifier circuit path said third sampled and held charge accumulated signal; and

amplifying through said second amplifier circuit path said second sampled and held reset signal after said step of amplifying through said second amplifier circuit path said fourth sampled and held charge accumulated signal.

64. An imager, comprising:

a pixel array including a first plurality of columns of pixels;

a first shared column amplifier circuit for receiving signals from a first subset of columns of said first plurality of columns, said first shared column amplifier circuit comprising;

a first image signal circuit for sampling and holding an image signal from a first desired pixel in a first column of said first subset of columns of said pixel array;

a second image signal circuit for sampling and holding an image signal from a second desired pixel in a second column of said first subset of columns of said pixel array;

a first reset signal circuit for sampling and holding a reset signal from one of said first desired and second desired pixels, said first shared column amplifier configured to sequentially amplify said first image signal and said first reset signal, said first shared column amplifier configured to sequentially amplify said second image signal and said first reset signal;

a second shared column amplifier circuit for receiving signals from a second subset of said first plurality of columns, said first subset of columns being mutually exclusive from second subset of columns, said second shared column amplifier circuit comprising;

a third image signal circuit for sampling and holding an image signal from a third desired pixel in a first column of said second subset of columns of said pixel array; and

a fourth image signal circuit for sampling and holding an image signal from a fourth desired pixel in a second column of said second subset of columns of said pixel array.

65. The imager of claim 64, wherein said second shared column amplifier circuit further comprises:

a third reset signal circuit for sampling and holding a reset signal from said first desired pixel in said second subset of columns of said pixel array; and

a fourth reset signal circuit for sampling and holding a reset signal from said second desired pixel in said second column of said second subset of columns of said pixel array.