Memory cell array

• US 7,471,547 B2
• Filed: 11/27/2007
• Issued: 12/30/2008
• Est. Priority Date: 12/07/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Schloesser, Till
• Primary Examiner(s): Luu; Pho M.
• Application Number:
  US11/945,437
• Publication Number:
  US 20080089114A1
• Time in Patent Office: 399 Days
• Field of Search: 365/154, 365/149, 365/150
• US Class Current: 365/154
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells to corresponding bit lines via bit line contacts, and the transistors are addressed by the word lines. The bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line. Neighboring bit line contacts which are connected with one active area line are connected with neighboring bit lines. Consequently, one active area line is crossed by a plurality of bit lines.

Claims

1. An integrated circuit including a memory cell array comprising:

memory cells, each of the memory cells comprising a storage element and an access transistor;

bit lines running along a first direction;

word lines running along a second direction that is transverse the first direction; and

active areas being aligned along straight lines, the access transistors being at least partially formed in the active areas and electrically coupling corresponding storage elements to corresponding bit lines via bit line contacts, the transistors being addressed by the word lines;

wherein the bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line; and

wherein neighboring bit line contacts, each of which is connected to one of the straight lines, are connected with neighboring bit lines and wherein each of the memory cells is coupled to one bit line.

2. The integrated circuit according to claim 1, wherein the active areas comprise continuous active area lines.

3. The integrated circuit according to claim 2, further comprising isolation gate lines that are configured to isolate neighboring transistors from each other, the isolation gate lines being arranged in parallel with the word lines.

4. The integrated circuit according to claim 3, wherein two word lines are followed by one isolation gate line, and one isolation gate line is followed by two word lines.

5. The integrated circuit according claim 1, wherein each of the storage elements comprises a storage capacitor.

6. The integrated circuit according to claim 5, wherein the storage capacitor comprises a stacked capacitor.

7. The integrated circuit according to claim 6, wherein an angle between the active area lines and the bit lines is between approximately 10°

to 25°

.

8. The integrated circuit according to claim 7, wherein an angle between the active area lines and the bit lines is between approximately 18°

to 19°

.

9. The integrated circuit according to claim 1, wherein one bit line contact is associated with two neighboring transistors that are formed in one active area.

10. An integrated circuit including a memory cell array comprising:

memory cells, each of the memory cells comprising a storage element and an access transistor;

bit lines running along a first direction;

word lines running along a second direction that is transverse the first direction; and

active areas extending in a direction that is slanted with respect to the first and second directions, gate electrodes of the access transistors being disposed in gate grooves that are formed in the active areas, the access transistors electrically coupling corresponding storage elements to corresponding bit lines via bit line contacts, the transistors being addressed by the word lines;

wherein the bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line; and

wherein neighboring bit line contacts, that are shifted along a direction that is slanted with respect to the first and second directions, are connected with neighboring bit lines and wherein each of the memory cells is coupled to one bit line.

11. The integrated circuit according to claim 10, wherein the active areas comprise continuous lines.

12. The integrated circuit according to claim 10, wherein the continuous lines comprise straight lines.

13. The integrated circuit according to claim 10, wherein each of the storage elements comprises a storage capacitor.

14. The integrated circuit according to claim 13, wherein the storage capacitor comprises a stacked capacitor.

15. The integrated circuit according to claim 14, wherein an angle between the active area lines and the bit lines is between approximately 10°

to 25°

.

16. The integrated circuit according to claim 10, wherein one bit line contact is associated with two neighboring transistors that are formed in one active area.

17. The integrated circuit according to claim 10, further comprising isolation gate lines that are configured to isolate neighboring transistors from each other, the isolation gate lines being arranged in parallel with the word lines.

18. An integrated circuit including a memory cell away comprising:

bit lines running along a first direction;

word lines running along a second direction that is transverse the first direction, the word lines being buried in a semiconductor substrate;

active areas being formed in the semiconductor substrate; and

access transistors of the memory cells being at least partially formed in the active areas, the access transistors being addressed by the word lines;

wherein the active areas extend in a direction that is slanted with respect to the first and second directions, respectively.

19. The integrated circuit according to claim 18, wherein the active areas extend along straight lines.

20. An integrated circuit comprising a transistor, the transistor comprising:

a first and a second source/drain portions; and

a gate electrode, the gate electrode including;

a gate groove disposed in a semiconductor substrate at a position between the first and the second source/drain portions, and

a conductive material disposed in the gate groove,

wherein an insulating material is disposed in the gate groove above the conductive material, the insulating material being configured to electrically isolate the gate electrode from the first and the second source/drain portions.

21. The integrated circuit of claim 20, wherein the conductive material comprises a metal.

22. The integrated circuit of claim 20, wherein the first and the second source/drain portions are disposed adjacent to a horizontal surface of the semiconductor substrate.

23. The integrated circuit of claim 20, wherein a lower surface of the insulating material is disposed at approximately the same level as the lower boundary of the first and second source/drain portions.

24. The integrated circuit of claim 20, wherein the upper portion of the gate groove is completely filled with the insulating material.

25. The integrated circuit of claim 20, wherein an upper surface of the insulating material is disposed above a surface of the semiconductor substrate.