Local bank write buffers for accelerating a phase-change memory

• US 7,471,556 B2
• Filed: 05/15/2007
• Issued: 12/30/2008
• Est. Priority Date: 05/15/2007
• Status: Expired due to Fees

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Yu, Frank I-Kang, Lee, Charles C., Chow, David Q.
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US11/748,595
• Publication Number:
  US 20080285334A1
• Time in Patent Office: 595 Days
• Field of Search: 365/163, 365/230.03, 365/189.05, 365/230.06
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell'"'"'s set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data. The very long write-1 time may require wait states. To eliminate wait states for sequential accesses, the PCM cells are divided into 16 banks. Each bank has its own bank write latch that stores data locally at the bank while the bank is being written. Data lines to the banks are freed up to transfer data to other banks once the data is written into the local bank write latch, allowing the long set-current pulse to be applied locally to slowly grow crystals in the alloy resistors. External host data are buffered and applied to the data lines by an array data mux.

Claims

1. A locally-latched phase-change memory (PCM) comprising:

a data input that receives a data word in response to a write request and a write address;

a data output that outputs a data word in response to a read request and a read address;

a host write buffer, coupled to the data input, for storing the data word;

a plurality of PCM cells each having a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase;

a plurality of banks, each bank comprising;

an array of the plurality of PCM cells;

an X decoder, receiving an X portion of the write address or receiving an X portion of the read address, for selecting a row of the PCM cells selected by an activated word line selected from a plurality of word lines in the array;

a Y decoder, receiving a Y portion of the write address or receiving a Y portion of the read address, for selecting a column of the PCM cells in the array as selected PCM cells;

local sense amplifiers for reading read data stored in the selected PCM cells in response to the read address;

local write drivers for driving a set pulse for a set period of time to the selected PCM cells that are being written to the first logical state, and for driving a reset pulse for a reset period of time to the selected PCM cells that are being written to the second logical state;

local bank write latches, storing write data that includes set data bits indicating the first logical state and reset data bits indicating the second logical state, the local bank write latches coupled to control the local write drivers to drive the set pulse and the reset pulse to the selected PCM cells; and

shared data lines, driven by the host write buffer, for transferring write data from the data word in the host write buffer to the local bank write latches for a selected bank in the plurality of banks, wherein the selected bank is selected by a bank portion of the write address;

an array data mux that disconnects the shared data lines from the local bank write latches of a prior selected bank before the set and reset pulses are applied to the selected PCM cells, allowing data transfer to the selected bank while the set and reset pulses are being applied to the prior selected bank,

whereby set and reset pulses are driven to the selected PCM cells from data stored in the local bank write latches, freeing the shared data lines when the set and reset pulses are applied.

2. The locally-latched phase-change memory of claim 1 wherein a PCM cell in the plurality of PCM cells comprises:

a select transistor receiving a word line on a gate, and having a channel between a bit line and a cell node;

an alloy resistor formed from the alloy, coupled between the cell node and an array voltage;

wherein the PCM cell has the first logical state when the alloy resistor has the alloy in the crystalline phase, the alloy resistor having a low resistance that increases a sensing current from the bit line through the select transistor;

wherein the PCM cell has the second logical state when the alloy resistor has the alloy in the amorphous phase, the alloy resistor having a high resistance that reduces the sensing current from the bit line through the select transistor;

wherein the high resistance is larger than the low resistance;

whereby the sensing current is altered by the alloy being in the crystalline phase and the amorphous phase.

3. The locally-latched phase-change memory of claim 2 wherein the local write drivers further comprise:

a set current generator, coupled to the bit line, for driving a set current through the select transistor and through the alloy resistor for a set period of time to write the PCM cell into the first logical state in response to set data bits in the local bank write latches;

a reset current generator, coupled to the bit line, for driving a reset current through the select transistor and through the alloy resistor for a reset period of time to write the PCM cell into the second logical state in response to reset data bits in the local bank write latches;

a reset timer for determining the reset period of time; and

a set timer for determining the set period of time;

wherein the set period of time is at least double the reset period of time,

whereby the PCM cell is set for a longer time period, and reset for a shorter time period.

4. The locally-latched phase-change memory of claim 3 wherein the reset current is at least twice the set current, and wherein the set current is at least twice the sensing current;

whereby the PCM cell is set by a lower current for a longer time period, and reset by a higher current and a shorter time period.

5. The locally-latched phase-change memory of claim 4 wherein the alloy is a chalcogenide glass layer having a melting point that is higher than a crystallization point.

6. The locally-latched phase-change memory of claim 5 wherein the alloy is an alloy of germanium (Ge), antimony (Sb), and tellurium (Te).

7. The locally-latched phase-change memory of claim 5 wherein the plurality of banks comprises 16 banks.

8. The locally-latched phase-change memory of claim 7 wherein the local bank write latches store a byte of write data for each bank in the plurality of banks.

9. The locally-latched phase-change memory of claim 5 wherein the selected PCM cells comprises 8 selected PCM cells.

10. The locally-latched phase-change memory of claim 5 wherein the host write buffer comprises a plurality of buffers each for a different access request.

11. The locally-latched phase-change memory of claim 5 wherein the bank portion of the write address comprises a least-significant-bit (LSB) portion of the write address;

whereby the plurality of banks are LSB interleaved.

12. The locally-latched phase-change memory of claim 5 wherein each bank in the plurality of banks further comprises:

local read latches, coupled to the local sense amplifiers, for locally storing read data.

13. The locally-latched phase-change memory of claim 12 further comprising:

read data lines, coupled to the local read latches, for transferring the read data to the data output in response to the read request,

whereby separate data lines for read and write are provided.

14. The locally-latched phase-change memory of claim 5 wherein each bank in the plurality of banks has an array of the plurality of PCM cells that comprises an array of 256 rows and 32 columns.

15. A memory system comprising:

phase-change memory means for storing a data word data as binary bits each represented by a chalcogenide glass layer having a melting point that is higher than a crystallization point, the chalcogenide glass layer forming a variable resistor that alters a sensing current when a binary bit is read;

wherein a crystalline state of the variable resistor represents a first binary logic state and an amorphous state of the variable resistor represents a second binary logic state for binary bits stored in the phase-change memory means;

bus I/O means for receiving a data I/O word from a host in response to a write request from the host, and for outputting a data I/O word to the host in response to a read request from the host;

I/O buffer means for storing the data I/O word received from the host by the bus I/O means until a data word is accumulated;

a plurality of bank means for storing interleaved data, each bank means comprising;

an array formed of a plurality of cells of the phase-change memory means, the array having rows and columns;

row decoder means, receiving a row address, for selecting a selected row of the plurality of cells in response to the row address;

column decoder means, receiving a column address, for selecting a selected column of the plurality of cells in response to the column address;

wherein selected cells of the phase-change memory means in the array are at an intersection of the selected row and the selected column;

bank write latch means for storing data bits to write into the selected cells;

sense amplifier means for reading data stored in the selected cells by sensing a difference in resistance of the variable resistor when in the crystalline state and when in the amorphous state; and

data line transfer means, coupled between the I/O buffer means and the bank write latch means in the plurality of bank means, for transferring portions of the data word stored in the I/O buffer means to the bank write latch means of a second bank means in the plurality of bank means while the bank write latch means in a first bank means in the plurality of bank means is writing data into the selected cells,

whereby bank writing occurs concurrently with data transfer to another bank.

16. The memory system of claim 15 wherein each bank means further comprises:

set current timer means, coupled to the bank write latch means, for applying a set current for a set period of time to the selected cells to set variable resistors into the crystalline state when the binary bits being written are in the first binary logic state;

reset current timer means, coupled to the bank write latch means, for applying a reset current for a reset period of time to the selected cells to reset variable resistors into the amorphous state when the binary bits being written are in the second binary logic state;

wherein the reset current is at least twice the set current, and wherein the set current is at least twice a sensing current that passes through the variable resistor during a read operation;

wherein the set period of time is at least double the reset period of time,

whereby the variable resistor is set by a lower current for a longer time period, and reset by a higher current and a shorter time period.

17. The memory system of claim 16 wherein the data word stored in the phase-change memory means is retained when power is suspended,

whereby the data word is stored in non-volatile memory.

18. A phase-change memory with local write buffering comprising:

a plurality of banks of memory cells, each bank in the plurality of banks having an array of memory cells;

an alloy resistor in each memory cell in each array of memory cells, the alloy resistor storing binary data as solid phases each having a different resistivity;

wherein the alloy resistor changes from a crystalline state to an amorphous state when a memory cell is written from a logic 1 state to a logic 0 state in response to a reset current for a reset period of time;

wherein the alloy resistor changes from the amorphous state to the crystalline state when the memory cell is written from a logic 0 state to a logic 1 state in response to a set current for a set period of time;

wherein the amorphous state has a higher resistance than the crystalline state that is sensed by a sense amplifier;

a data input for receiving a data word to store in the phase-change memory;

a write buffer, coupled to the data input to receive the data word;

data lines coupled between the write buffer and the plurality of banks of memory cells, for transferring the data word to the plurality of banks;

a plurality of bank write latches, wherein each bank in the plurality of banks has a local bank write latch that receives a bank portion of the data word from the data lines;

a plurality of write drivers, wherein each bank in the plurality of banks has a local write driver that applies the set current for the set period of time to memory cells being written by bits in the logic 1 state in the bank portion of the data word stored in the local bank write latches, and that applies the reset current for the reset period of time to memory cells being written by bits in the logic 0 state in the bank portion of the data word stored in the local bank write latches;

wherein the set period of time is at least 5 times longer than the reset period of time;

wherein unequal set and reset pulses are applied to the alloy resistors to for changes between the crystalline state and the amorphous state; and

a plurality of bank sense amplifiers, wherein each bank in the plurality of banks has a local bank sense amplifier that senses data stored in selected memory cells by sensing currents passing through alloy resistors having a higher resistance when in the amorphous state than when in the crystalline state;

wherein the bank portion of the data word is written from the local bank write latches into the memory cells while the data lines are disconnected from writing the local bank write latches, the data lines able to transfer data to other banks in the plurality of banks while the data word is written from the local bank write latches into the memory cells,

whereby concurrent writes and data transfers to different banks are performed.

19. The phase-change memory with local write buffering of claim 18 wherein the set period of time is about 100 nanoseconds.

20. The phase-change memory with local write buffering of claim 18 wherein the data word stored in the memory cells is retained when power is disconnected,

wherein the alloy resistors remain in the amorphous state and remain in the crystalline state when power is disconnected;

whereby the data word is stored in non-volatile memory.