Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory
First Claim
Patent Images
1. A data storage system comprising:
- a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each memory cell being configurable to store one of a plurality of reference signal levels;
a plurality of reference sense amplifiers, each reference sense amplifier being selectively coupled to a corresponding subarray; and
a capacitor configured to provide an autozero mode via an autozeroing comparison circuit to capacitively sense content of a memory cell.
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Abstract
A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
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Citations
31 Claims
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1. A data storage system comprising:
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a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each memory cell being configurable to store one of a plurality of reference signal levels; a plurality of reference sense amplifiers, each reference sense amplifier being selectively coupled to a corresponding subarray; and a capacitor configured to provide an autozero mode via an autozeroing comparison circuit to capacitively sense content of a memory cell. - View Dependent Claims (3, 4, 5, 10, 11, 21, 22, 23, 24)
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2. A data storage system comprising:
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a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each reference memory cell being configurable to store one of a plurality of reference signal levels; and a plurality of reference sense amplifiers, each sense reference amplifier being selectively coupled to a reference memory subarray to sense, via offset autozeroing comparison circuitry, content of a reference memory cell. - View Dependent Claims (12, 15, 25, 26, 27, 28, 29, 30, 31)
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6. A data storage system comprising:
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a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each memory cell being configurable to store one of a plurality of reference signal levels; a plurality of reference sense amplifiers, each reference sense amplifier being selectively coupled to a corresponding subarray; and a capacitor configured to capacitively sense content of a memory cell; wherein the reference sense amplifier capacitively detects a signal on a bitline and a reference signal and generates an output signal indicative of the comparison between said detected signal in a selected reference cell and said detected reference signal. - View Dependent Claims (7, 8, 9)
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13. A data storage system comprising:
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a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each reference memory cell being configurable to store one of a plurality of reference signal levels; and a plurality of reference sense amplifiers, each sense reference amplifier being selectively coupled to a reference memory subarray to sense with offset autozeroing content of a reference memory cell; wherein at least one reference sense amplifier includes a circuit for coupling inputs of the at least one reference sense amplifier to an output signal in response to an autozero signal. - View Dependent Claims (14)
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16. A data storage system comprising:
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a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each reference memory cell being configurable to store one of a plurality of reference signal levels; a plurality of reference sense amplifiers, each sense reference amplifier being selectively coupled to a reference memory subarray to sense with offset autozeroing content of a reference memory cell; and a reference array operatively coupled to the reference memory subarrays and configurable to provide stored reference signals used for programming and reading selected reference memory cells, the stored reference signals corresponding to detected reference signals; wherein each reference sense amplifier autozeros an input and output in order to zero out offset of reference sense circuitry.
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17. A data storage system comprising:
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a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each reference memory cell being configurable to store one of a plurality of reference signal levels; a plurality of reference sense amplifiers, each sense reference amplifier being selectively coupled to a reference memory subarray to sense with offset autozeroing content of a reference memory cell; and a reference array operatively coupled to the reference memory subarrays and configurable to provide stored reference signals used for programming and reading selected reference memory cells, the stored reference signals corresponding to detected reference signals; wherein at least one reference sense amplifier includes a circuit for coupling inputs of the at least one reference sense amplifier to an output signal in response to an autozero signal. - View Dependent Claims (18)
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19. A data storage system comprising:
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a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each reference memory cell being configurable to store one of a plurality of reference signal levels; a plurality of reference sense amplifiers, each sense reference amplifier being selectively coupled to a reference memory subarray to sense with offset autozeroing content of a reference memory cell; and a circuit to set an input and an output of reference circuitry in response to an autozero signal. - View Dependent Claims (20)
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Specification