Methods and arrangements for link power reduction
First Claim
1. An apparatus for reducing power consumption by a clock and data recovery loop circuit, comprising:
- a flywheel to monitor adjustments made in a phase of a sampling clock by a phase controller, the sampling clock being generated to sample bit values from a data signal, and to modify the adjustments in the phase of the sampling clock to track a phase of the data signal; and
a loop latency controller to monitor the modifications of the adjustments to the phase of the sampling clock, to determine the existence of spread spectrum clocking based upon a pattern of the modifications, and, in response, to adapt a stage of the clock and data recovery loop circuit to operate with less power consumption.
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Abstract
Methods, and arrangements for extension of clock and data recovery (CDR) loop latency and deactivation of CDR circuits are disclosed. In particular, embodiments address situations in which a receiver, designed to handle spread spectrum clocking, may not always or continuously encounter spread spectrum signals. As a result, power consumption by the receivers may be reduced. Embodiments identify situations in which spread spectrum clocking is unnecessary and may adapt the CDR loop to operate with less power consumption by, e.g., reducing the operating frequency of CDR circuits. For instance, some embodiments employ a flywheel circuit, incorporated into many spread spectrum CDR loops to accelerate adjustments to a sampling clock, to determine when spread spectrum signals are not being encountered. A loop latency controller may then, advantageously, reduce power consumption by reducing frequencies of operation and voltages, and merging or simplifying stages.
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Citations
14 Claims
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1. An apparatus for reducing power consumption by a clock and data recovery loop circuit, comprising:
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a flywheel to monitor adjustments made in a phase of a sampling clock by a phase controller, the sampling clock being generated to sample bit values from a data signal, and to modify the adjustments in the phase of the sampling clock to track a phase of the data signal; and a loop latency controller to monitor the modifications of the adjustments to the phase of the sampling clock, to determine the existence of spread spectrum clocking based upon a pattern of the modifications, and, in response, to adapt a stage of the clock and data recovery loop circuit to operate with less power consumption. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A clock and data recovery loop circuit, comprising:
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a clock generator to generate a sampling clock; sampling circuitry to sample values for a bit from a data signal based upon the sampling clock; comparison circuitry to compare the values for the bit to generate a comparison signal indicative of a difference between the phase of the sampling clock and the phase of the data signal; a phase controller to adjust the phase of sampling clock in response to the comparison signal; a flywheel to monitor adjustments in the phase of the sampling clock by the phase controller and to modify the adjustments in the phase of the sampling clock to track the phase of the data signal; and a loop latency controller to monitor the modifications of the adjustments in the phase of the sampling clock, to determine the existence of spread spectrum clocking based upon a pattern of the modifications, and, in response, to adapt a stage of the clock and data recovery loop circuit to operate with less power consumption. - View Dependent Claims (11, 12, 13, 14)
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Specification