Apparatus to offload and accelerate pico code processing running in a storage processor

• US 7,472,237 B1
• Filed: 10/28/2003
• Issued: 12/30/2008
• Est. Priority Date: 10/28/2002
• Status: Active Grant

• Current Assignee: NetApp, Inc.
• Original Assignee: NetApp, Inc.
• Inventors: Cihla, James L., Ibrahim, Rahim, Herbst, Ryan Taylor, Vuong, James L.
• Primary Examiner(s): Peugh; Brian R
• Application Number:
  US10/696,624
• Time in Patent Office: 1,890 Days
• Field of Search: 711/152, 711163-164, 710/200, 707/8
• US Class Current: 711/152
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields

Abstract

Apparatus and method offloads processing from a networking processor operating in a storage environment. Three main functions are offloaded: semaphore processing, frame order processing, and timer processing. Offloading of semaphore processing enables ordered access to semaphores. Offloading of frame order processing enables the network processor to quickly transmit an incoming frame if the incoming frame is the next one in the frame order. Offloading of timer processing enables background checking of the timer list.

Claims

1. A processor for offloading processing in a storage environment, comprising:

a zero bus turnaround (“

ZBT”

) interface that interfaces said processor to a network processor configured to perform a storage function;

a hash bucket memory having an array of bit-bucket pointers that each operate as a head pointer to a linked list of active semaphore structures, the hash bucket memory addressable by a hash address derived through application of a hash function to a semaphore value and wherein each semaphore structure accommodates a current thread that owns a semaphore and potentially one or more waiting threads in a queue waiting for release of the semaphore;

semaphore circuitry, coupled to said ZBT interface, that receives a signal from said network processor, and that controls said semaphore associated with the corresponding predetermined linked list of active semaphore structures in the hash bucket memory wherein the received signal and said semaphore are related to locking and unlocking access to data in the storage environment; and

an update engine, further included in the semaphore circuitry, that upon receipt of a received signal from said network processor relating to a thread on said network processor, processes said semaphore related to said received signal and responds, as required, by sending a transmitted signal back to said network processor in association with said semaphore.

2. The processor of claim 1, wherein said update engine in the semaphore circuitry manages access to said semaphore by performing at least one command selected from a set of semaphore commands including:

a semaphore request, a semaphore release and a thread exit.

3. The processor of claim 1, wherein said update engine in the semaphore circuitry receives a second signal from said network processor and removes a request from said queue in response to said second signal when said network processor no longer desires said semaphore.

4. The processor of claim 1, wherein said update engine in the semaphore circuitry refrains from sending to said network processor a second signal indicating said semaphore is unavailable, whereby said network processor continues to wait for said semaphore and said semaphore circuitry maintains ordered access to said queue.

5. The processor of claim 1, wherein said signal comprises one of a plurality of access requests for one of a plurality of semaphores, wherein said semaphore circuitry manages said plurality of access requests in a plurality of queues, and wherein each of said plurality of queues corresponds to a respective one of said plurality of semaphores.

6. The processor of claim 1, wherein said semaphore circuitry comprises:

a command queue that stores said signal received from said network processor.

7. The processor of claim 1, wherein said semaphore is associated with a semaphore structure in the array of bit-bucket pointers in the hash bucket memory and wherein said semaphore circuitry comprises:

a hash key generator that performs a hashing function on said signal for accessing said hash array.

8. The processor of claim 1, wherein said update engine in the semaphore circuitry receives a second signal from said network processor relating to a first process thread on said network processor, releases a lock on said semaphore related to said second signal, and sends a third signal to said network processor associating said semaphore with a second process thread on said network processor.

9. The processor of claim 1, wherein said update engine in the semaphore circuitry further comprises:

a semaphore queue manager that manages a queue of a plurality of semaphores.

10. The processor of claim 1, wherein said semaphore circuitry manages a queue for access to said semaphore, wherein said semaphore circuitry comprises:

a hash key generator that performs the hashing function on said signal for accessing the hash bucket memory having an array of bit-bucket pointers, and that generates a hash key related to said signal, wherein said semaphore is associated with a semaphore structure in said array of bit-bucket pointers, and wherein said signal relates to a first process thread on said network processor; and

the update engine, coupled to said hash key generator, that receives said hash key, that releases a lock on said semaphore related to said hash key, and that sends a second signal to said network processor associating said semaphore with a second process thread on said network processor, wherein said first process thread and said second process thread are associated with said semaphore in said queue.

11. A method of controlling a processor for offloading processing in a storage environment, comprising the steps of:

receiving a signal from a network processor configured to perform a storage function through a zero bus turnaround (“

ZBT”

) interface;

assigning a current thread as owner of a semaphore and potentially one or more waiting threads in a queue waiting for release of the semaphore to a semaphore structure in a linked list of active semaphore structures stored in a hash bucket memory addressable through application of a hash function to a semaphore value associated with the semaphore;

controlling said semaphore associated with the linked list of active semaphore structures in the hash bucket memory wherein the received signal and the semaphore are related to locking and unlocking access to data in the storage environment; and

processing the received signal from said network processor relating to a thread on said network processor and responding, as required, by sending a transmitted signal back to said network processor in association with said semaphore.

12. The method of claim 11, wherein said step of controlling said semaphore further includes managing access to said semaphore by performing at least one command selected from a set of commands including:

a semaphore request, a semaphore release and a thread exit.

13. The method of claim 11, further comprising:

receiving a second signal from said network processor; and

removing a request from said queue in response to said second signal when said network processor no longer desires said semaphore.

14. The method of claim 11, further comprising:

refraining from sending to said network processor a second signal indicating said semaphore is unavailable, whereby said network processor continues to wait for said semaphore and said processor maintains ordered access to said queue.

15. The method of claim 11, wherein said signal comprises one of a plurality of access requests for one of a plurality of semaphores, and wherein said step of controlling said semaphore includes:

managing said plurality of access requests in a plurality of queues, wherein each of said plurality of queues corresponds to a respective one of said plurality of semaphores.

16. The method of claim 11, wherein said step of controlling said semaphore includes:

receiving a second signal from said network processor relating to a first process thread on said network processor;

releasing a lock in said semaphore related to said second signal; and

sending a third signal to said network processor associating said semaphore with a second process thread on said network processor.

17. The method of claim 11, wherein said signal comprises one of a plurality of access requests for one of a plurality of semaphores, and wherein said step of controlling said semaphore includes:

managing said plurality of access requests in a plurality of queues, wherein each of said plurality of queues corresponds to a respective one of said plurality of semaphores;

receiving a second signal from said network processor relating to a first process thread on said network processor;

releasing a lock on said semaphore related to said second signal; and

sending a third signal to said network processor associating said semaphore with a second process thread for said network processor.