Debugging mechanism and debugging register
First Claim
1. A debugging mechanism in a system in which a plurality of bus masters share a common bus slave, the debugging mechanism comprising:
- a bus control unit for supporting the plurality of bus masters, registering details of write access requested from each bus master upon receiving the write access, and performing a release control of notifying each bus master of completion of access before completion of access to the bus slave and an access order control of not ensuring an execution order of bus access among the plurality of bus masters;
a debugging register for designating conditions of bus access subjected to debugging;
a dirty detector for constantly monitoring an operation of the bus control unit, detecting a period of status disparity between the bus master and the bus slave, the period ranging from registration of write access coincident with the conditions designated by the debugging register in the write buffer to completion of access to the bus slave, and sending a notification about the detected period; and
a debugging unit, provided at the bus master, for treating the notification about detection of the status disparity period received from the dirty detector as an AND condition in detection of a debugging event, whereinthe bus master provided with the debugging unit breaks an operation thereof by using a debugging event generated in establishment of operational conditions optionally designated by the debugging unit, during the status disparity period.
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Accused Products
Abstract
The present invention aims at providing a debugging mechanism capable of detecting erroneous read access to a bus slave caused by a synchronization control infringement between bus masters due to a failure of software. Each of a dirty detector and a coherency error detector is used as a detector for monitoring a bus control unit and, during a period that write access corresponding to optionally designated conditions is present on a write buffer, detecting read access corresponding to conditions equal to the aforementioned conditions. A bus master includes a debugging unit. The debugging unit receives a coherency error notification from the coherency error detector to generate a debugging event, breaks an operation of the bus master, and performs various debugging operations while using the debugging event as a trigger.
7 Citations
8 Claims
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1. A debugging mechanism in a system in which a plurality of bus masters share a common bus slave, the debugging mechanism comprising:
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a bus control unit for supporting the plurality of bus masters, registering details of write access requested from each bus master upon receiving the write access, and performing a release control of notifying each bus master of completion of access before completion of access to the bus slave and an access order control of not ensuring an execution order of bus access among the plurality of bus masters; a debugging register for designating conditions of bus access subjected to debugging; a dirty detector for constantly monitoring an operation of the bus control unit, detecting a period of status disparity between the bus master and the bus slave, the period ranging from registration of write access coincident with the conditions designated by the debugging register in the write buffer to completion of access to the bus slave, and sending a notification about the detected period; and a debugging unit, provided at the bus master, for treating the notification about detection of the status disparity period received from the dirty detector as an AND condition in detection of a debugging event, wherein the bus master provided with the debugging unit breaks an operation thereof by using a debugging event generated in establishment of operational conditions optionally designated by the debugging unit, during the status disparity period. - View Dependent Claims (2)
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3. A debugging mechanism in a system in which a plurality of bus masters share a common bus slave, the debugging mechanism comprising:
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a bus control unit for supporting the plurality of bus masters, registering details of write access requested from each bus master upon receiving the write access, and performing a release control of notifying each bus master of completion of access before completion of access to the bus slave and an access order control of not ensuring an execution order of bus access among the plurality of bus masters; a debugging register for designating conditions of bus access subjected to debugging; a dirty detector for constantly monitoring an operation of the bus control unit, detecting a period of status disparity between the bus master and the bus slave, the period ranging from registration of write access coincident with the conditions designated by the debugging register in the write buffer to completion of access to the bus slave, and sending a notification about the detected status disparity period; a coherency error detector for constantly monitoring an operation of the bus control unit, detecting a read access request coincident with conditions optionally designated by the debugging register, and sending a notification to a bus master requesting read access that read access has been executed to the bus slave optionally designated by the debugging register during the status disparity period, by using the detected result and the notification about the status disparity period detected by the dirty detector read access to the bus slave optionally designated by the debugging register; and a debugging unit provided at the bus master, for receiving a coherency error notification from the coherency error detector and generating a debugging event, wherein the debugging unit breaks the operation of the bus master by using the debugging event generated due to reception of the coherency error notification from the coherency error detector. - View Dependent Claims (4, 5, 6, 7, 8)
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Specification