Method and structure for implementing secure multichip modules for encryption applications

• US 7,472,836 B2
• Filed: 06/26/2007
• Issued: 01/06/2009
• Est. Priority Date: 04/14/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pompeo, Frank L., Fasano, Benjamin V., Ray, Sudipta K., Farooq, Mukta G., Long, David C., Hamel, Harvey C., Frankel, Jason L., Kadakia, Suresh D.
• Primary Examiner(s): St. Cyr; Daniel
• Application Number:
  US11/768,312
• Publication Number:
  US 20080000988A1
• Time in Patent Office: 560 Days
• Field of Search: 235/492, 235/487, 235/494
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07381 with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0275 Security details, e.g. tampering prevention or detection
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/09263 Meander
• CPC Class Codes: H05K 2201/10151 Sensor

Abstract

A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Claims

1. A method for forming a tamper resistant, integrated circuit (IC) module, the method comprising:

embedding a conductive grid structure within both a ceramic-based chip carrier and a ceramic based cap structure, said conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction;

attaching one or more integrated circuit chips to a top surface chip carrier; and

attaching the cap structure to the top surface of the chip carrier;

wherein said conductive grid structure is configured to determine an attempt to penetrate the IC module by detecting at least one of a change in resistance and a change in capacitance of said conductive grid structure.

2. The method of claim 1, further comprising adhering the cap structure to the chip carrier with a polymeric adhesive layer between a footing of the cap structure and the chip carrier, wherein said footing surrounds the one or more IC chips attached to the chip carrier.

3. The method of claim 1, further comprising:

forming a plurality of solder fillets along an outer perimeter and an inner perimeter of said footing, said solder fillets configured to provide electrical connection between internal wiring of the cap structure and internal wiring of the chip carrier;

wherein said plurality of solder fillets on said outer perimeter and said plurality of solder fillets on said inner perimeter are positioned interstitially with respect to one another.

4. The method of claim 1, wherein meandering lines formed on one wiring level of said chip carrier are disposed in an offset arrangement with respect to meandering lines formed on an adjacent wiring level of said chip carrier, and wherein said plurality of meandering lines in said x-direction and said y-direction are formed at a selected linewidth and pitch therebetween, such that said offset arrangement results in an effective pitch in said z-direction equal to or less than said selected linewidth.

5. The method of claim 1, wherein said meandering lines in said z-direction further comprise jogs formed on one level of said chip carrier coupled to jogs formed on another level of said chip carrier through conductively filled vias.