Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same

• US 7,473,589 B2
• Filed: 10/13/2006
• Issued: 01/06/2009
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting, Lai, Erh Kun, Hsieh, Kuang Yeu
• Primary Examiner(s): Nhu; David
• Application Number:
  US11/549,520
• Publication Number:
  US 20070134876A1
• Time in Patent Office: 816 Days
• Field of Search: 438/149, 438/238, 438/381, 438/257, 438/311, 438/261, 438/724, 438/745, 438/752, 438/763, 438/687, 438/688, 438/933, 438/954, 438/680
• US Class Current: 438/149
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A manufacturing method for stacked, non-volatile memory device provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures, orthoganal to the bitlines.

Claims

1. A method for fabricating a non-volatile memory device comprising a plurality of bitline layers and a plurality of wordline layers sequentially formed on top of each other, the method comprising:

forming the plurality of bitline layers layer, wherein forming each bitline layer comprises;

forming a semiconductor layer on an insulator, and

patterning and etching the semiconductor layer to form a plurality of bitlines;

forming word line layers in the plurality of wordline layers over respective preceding ones of the plurality of bitline layers, wherein forming each wordline layer comprises;

sequentially forming a trapping structure and a conducting layer, and

patterning and etching the trapping structure and the conducting layer to form a plurality of wordlines; and

forming source/drain regions in regions of the plurality of bitlines not covered by the plurality of wordlines with active regions in the plurality of bit lines beneath the plurality of wordlines.

2. The method of claim 1, wherein patterning and etching the semiconductor layer comprises:

forming a cap layer over the semiconductor layer;

etching the cap layer and the semiconductor layer to form bitline regions comprising remaining portions of the cap layer and the semiconductor layer;

forming a dielectric layer over the etched cap and semiconductor layers;

etching a portion of the dielectric layer to form dielectric region between the bitline regions and on top of the remaining portions of the cap layer; and

removing the remaining portions of the cap layer and removing the remaining portions of the dielectric layer on top of the cap layer.

3. The method of claim 2, wherein the cap layer comprises a nitride layer.

4. The method of claim 2, wherein the dielectric layer comprises silicon dioxide.

5. The method of claim 4, wherein the silicon dioxide is deposited using high density plasma, chemical vapor deposition.

6. The method of claim 1, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

7. The method of claim 1, wherein forming the trapping structure comprises forming an oxide-nitride-oxide (ONO), nitride read only memory structure.

8. The method of claim 1, wherein forming the trapping structure comprises forming a Band-gap Engineered (BE)-SONOS structure.

9. The method of claim 1, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-silicon (SONS) structure.

10. The method of claim 1, wherein forming the trapping structure comprises forming a top BE-SONOS structure.

11. The method of claim 1, wherein forming the trapping structure comprises forming a top silicon-oxide-nitride-oxide-silicon-oxide-silicon (SONOSOS) structure.

12. The method of claim 1, wherein forming the trapping structure comprises forming a bottom SOSONOS structure.

13. The method of claim 1, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-oxide-nitride-silicon (SONONS) structure.

14. The method of claim 1, wherein forming the trapping structure comprises forming a silicon nitride (SiN) layer.

15. The method of claim 1, wherein forming the trapping structure comprises forming a SiON layer.

16. The method of claim 1, wherein forming the trapping layer comprises depositing a Hi-K material.

17. The method of claim 16, wherein the Hi-K material is HfO₂, AlN, or Al₂O₃.

18. The method of claim 1, wherein the semiconductor layer comprises a P-type semiconductor material, and wherein forming the source drain regions comprises forming N+ regions in the P-type semiconductor material.

19. The method of claim 18, wherein the N+ regions are formed using As or P.

20. The method of claim 1, wherein the conducting layer comprises polysilicon material.

21. The method of claim 1, wherein the conducting layer comprises polysilicon/silicide/polysilicon material.

22. The method of claim 1, wherein the conducting layer comprises a metal.

23. The method of claim 22, wherein the metal is aluminum, copper, or tungsten.

24. The method of claim 1, wherein patterning and etching the trapping structure and conducting layer comprises:

forming a cap layer over the trapping structure and conducting layer;

etching the cap layer and the trapping structure and conducting layer to form wordline regions comprising remaining portions of the cap layer and the trapping structure and conducting layer;

forming a dielectric layer over the etched cap and trapping structure and conducting layers;

etching a portion of the dielectric layer to form dielectric regions between the wordlines and on top of the remaining portions of the cap layer; and

removing the remaining portions of the cap layer and removing the portions of the dielectric layer on top of the cap layer.

25. The method of claim 24, wherein the cap layer comprises a nitride layer.

26. The method of claim 24, wherein the dielectric layer comprises silicon dioxide.

27. The method of claim 26, wherein the silicon dioxide is deposited using high density plasma, chemical vapor deposition.

28. A method for fabricating a non-volatile memory device comprising a plurality of bitline layers and a plurality of wordline layers sequentially formed on top of each other, the method comprising:

forming the plurality of bitline layers, wherein forming each bitline layer comprises;

forming a first semiconductor layer on an insulator,

forming a cap layer over the semiconductor layer,

etching the cap layer and the first semiconductor layer to form bitline regions comprising remaining portions of the cap layer and the semiconductor layer,

forming a dielectric layer over the etched cap and semiconductor layers,

etching a portion of the dielectric layer to form dielectric regions between the bitline regions and dielectric regions on top of the remaining portions of the cap layer, and

removing the remaining portions of the cap layer and removing the remaining portions of the dielectric layer on top of the cap layer; and

forming the plurality of wordline layers over a preceding one of the plurality of bitline layers, wherein forming each wordline layer comprises;

sequentially forming a trapping structure and a conducting layer, the trapping structure comprising a multilayer structure, and

patterning and etching the trapping structure and the conducting layer to form a plurality of wordlines.

29. The method of claim 28, wherein the cap layer comprises a nitride layer.

30. The method of claim 28, wherein the dielectric layer comprises silicon dioxide.

31. The method of claim 30, wherein the silicon dioxide is deposited using high density plasma, chemical vapor deposition.

32. The method of claim 28, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

33. The method of claim 28, wherein forming the trapping structure comprises forming an oxide-nitride-oxide (ONO), nitride read only memory structure.

34. The method of claim 28, wherein forming the trapping structure comprises forming a Band-gap Engineered (BE)-SONOS structure.

35. The method of claim 28, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-silicon (SONS) structure.

36. The method of claim 28, wherein forming the trapping structure comprises forming a top BE-SONOS structure.

37. The method of claim 28, wherein forming the trapping structure comprises forming a top silicon-oxide-nitride-oxide-silicon-oxide-silicon (SONOSOS) structure.

38. The method of claim 28, wherein forming the trapping structure comprises forming a bottom SOSONOS structure.

39. The method of claim 28, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-oxide-nitride-silicon (SONONS) structure.

40. The method of claim 28, wherein forming the trapping structure comprises forming a silicon nitride (SiN) layer.

41. The method of claim 28, wherein forming the trapping structure comprises forming a SiON layer.

42. The method of claim 28, further comprising forming source/drain regions in the regions of the plurality of bitlines not covered by the plurality of wordlines.

43. The method of claim 42, wherein the semiconductor layer comprises a P-type semiconductor material, and wherein forming the source drain regions comprises forming N+ regions in the P-type semiconductor material.

44. The method of claim 43, wherein the N+ regions are formed using As or P.

45. The method of claim 28, wherein the conducting layer comprises polysilicon material.

46. The method of claim 28, wherein the conducting layer comprises polysilicon/silicide/polysilicon material.

47. The method of claim 28, wherein the conducting layer comprises a metal.