Semiconductor transistors with expanded top portions of gates

• US 7,473,593 B2
• Filed: 01/11/2006
• Issued: 01/06/2009
• Est. Priority Date: 01/11/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Victor W. C., Nowak, Edward Joseph, Anderson, Brent Alan
• Primary Examiner(s): Toledo; Fernando L.
• Assistant Examiner(s): Lee; Jae
• Application Number:
  US11/275,514
• Publication Number:
  US 20070158763A1
• Time in Patent Office: 1,091 Days
• Field of Search: 438/197, 438/299, 438/301
• US Class Current: 438/197
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A method for forming a semiconductor transistor with an expanded top portion of a gate The gate is expanded through implanting atoms in the top portion of transistor'"'"'s gate electrode region. The transistor formed includes a semiconductor region having two source/drain regions and a gate dielectric region formed on the channel region between the source/drain regions. The gate electrode region is formed on the gate dielectric region. The gate electrode region is formed such that it is electrically insulated from the channel region by the gate dielectric region. The top of the gate electrode region formed is wider than the bottom of the gate electrode region.

Claims

1. A semiconductor structure fabrication method, comprising:

providing a structure which comprises;

(a) a substrate which includes a top substrate surface, and a semiconductor region being on the top substrate surface, the semiconductor region including a channel region, a first source/drain region, and a second source/drain region, wherein the channel region is disposed between the first source/drain region and the second source/drain region,

wherein the top substrate surface defines a reference direction perpendicular to the top substrate surface,

(b) a gate dielectric region in direct physical contact with the channel region, and

(c) a gate electrode region including a top portion and a bottom portion,

wherein the bottom portion is disposed between the top portion and the gate dielectric region,

wherein the bottom portion is in direct physical contact with the gate dielectric region,

wherein the gate electrode region is electrically insulated from the channel region by the gate dielectric region, and

wherein the gate electrode region is formed by (i) providing a gate electrode layer; and

(ii) patterning the gate electrode layer resulting in the gate electrode region; and

after said providing the structure is performed, implanting atoms in the top portion of the gate electrode region resulting in the top portion of the gate electrode region being expanded in a lateral direction perpendicular to the reference direction, wherein said implanted atoms comprise germanium atoms;

after said implanting the atoms is performed, forming a conformal dielectric layer on top and side walls of the gate electrode region;

after said forming the conformal dielectric layer is performed, forming a dielectric spacer layer on the conformal dielectric layer; and

after said forming the dielectric spacer layer is performed, etching the dielectric spacer layer such that only spacer portions of the dielectric spacer layer which are under the conformal dielectric layer remain, wherein for any point of the remaining spacer portions, a straight line going through that point and being parallel to the reference direction intersects the conformal dielectric layer.

2. The method of claim 1, wherein said implanting the atoms is performed at an energy of about 25 KeV.

3. The method of claim 1, wherein said implanting the atoms is performed at about room temperature.

4. The method of claim 1,

wherein the structure further comprises a substrate,

wherein the substrate is in direct physical contact with the semiconductor region via a first interfacing surface that defines a normal direction perpendicular to the first interfacing surface, and

wherein said implanting the atoms is performed in a direction making with the normal direction an angle less than 10 degrees.

5. The method of claim 1, wherein the first width of the top portion and the second of the bottom portion are about the same before said implanting is performed.

6. The method of claim 1, further comprising, after said implanting the atoms is performed, forming silicide regions in the top portion of the gate electrode region and on the first source/drain region and the second source/drain region.

7. The method of claim 6,

wherein the top portion of the gate electrode region and the first and second source/drain regions comprise silicon, and

wherein said forming the suicide regions comprises:

depositing nickel on top of the structure; and

annealing the structure so that the nickel chemically reacts with the silicon of the top portion of the gate electrode region and the first and second source/drain regions to form the silicide regions.

8. The method of claim 1, wherein the structure further comprises a first extension region, a second extension region, a first halo region, and a second halo region,

wherein the first extension region is in direct physical contact with the channel region and the first source/drain region,

wherein the second extension region is in direct physical contact with the channel region and the second source/drain region,

wherein the first halo region is in direct physical contacts with the channel region, the first source/drain region and the first extension region, and

wherein the second halo region is in direct physical contacts with the channel region, the second source/drain region and the second extension region.

9. The method of claim 8, wherein the first and second source/drain regions, the first and second extension regions, and the first and second halo regions are formed by ion implantation.

10. The method of claim 1,

wherein the atoms are germanium atoms, and

wherein a first width of the top portion is at least 20% greater than a second width of the bottom portion.

11. The method of claim 10, wherein said implanting the atoms is performed at a dose of 10¹⁶ germanium atoms/cm².

12. The method of claim 10, further comprising implanting other atoms in the first and second source/drain regions to expand first and second upper portions of the first and second source/drain regions, respectively, wherein said implanting the atoms and said implanting the other atoms are performed simultaneously.

13. The method of claim 10, wherein the top portion of the gate electrode region comprises germanium and polysilicon.

14. A semiconductor structure fabrication method, comprising:

providing a structure which comprises;

(a) a substrate which includes a top substrate surface, and a semiconductor region being on the top substrate surface, the semiconductor region including a first portion, a second portion, and a channel region, wherein the channel region is disposed between the first and second portions, wherein the top substrate surface defines a reference direction perpendicular to the top substrate surface,

(b) a gate dielectric region in direct physical contact with the channel region, and

(c) a gate electrode region including a top portion and a bottom portion, wherein the bottom portion is in direct physical contact with the gate dielectric region, wherein the gate electrode region is electrically insulated from the channel region by the gate dielectric region, and wherein the gate electrode region is formed by (i) providing a gate electrode layer; and

(ii) patterning the gate electrode layer resulting in the gate electrode region; and

after said providing the structure is performed, implanting atoms in the top portion of the gate electrode region so as to expand the top portion of the gate electrode region in a lateral direction perpendicular to the reference direction, wherein said implanted atoms comprise germanium atoms;

after said implanting the atoms is performed, forming a conformal dielectric layer on top and side walls of the gate electrode region;

after said forming the conformal dielectric layer is performed, forming a dielectric spacer layer on the conformal dielectric layer; and

after said forming the dielectric spacer layer is performed, etching the dielectric spacer layer such that only spacer portions of the dielectric spacer layer which are under the conformal dielectric layer remain, wherein for any point of the remaining spacer portions, a straight line going through that point and being parallel to the reference direction intersects the conformal dielectric layer.

15. The method of claim 14, wherein a first width of the top portion is at least 20% greater than a second width of the bottom portion.

16. The method of claim 14, further comprising doping the first and second portion so as to form a first source/drain region and a second source/drain region, respectively.