Method for forming a shielded gate trench FET with the shield and gate electrodes being connected together

• US 7,473,603 B2
• Filed: 11/12/2007
• Issued: 01/06/2009
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Thorup, Paul, Kocon, Christopher Boguslaw, Kraft, Nathan
• Primary Examiner(s): Pham; Hoai v
• Application Number:
  US11/938,583
• Publication Number:
  US 20080064168A1
• Time in Patent Office: 421 Days
• Field of Search: 438/259, 438/270, 438/271, 438/589, 257/E21.655
• US Class Current: 438/259
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and a dielectric layer is formed along upper trench sidewalls and over the shield electrode. A gate electrode is formed in the trench over the shield electrode, and an interconnect layer connecting the gate electrode and the shield electrode is formed.

Claims

1. A method of forming a field effect transistor (FET), comprising:

forming a trench in a semiconductor region;

forming a shield dielectric layer lining lower sidewalls and a bottom surface of the trench;

forming a shield electrode in a lower portion of the trench;

forming a dielectric layer along upper trench sidewalls and over the shield electrode;

forming a gate electrode in the trench over the shield electrode; and

forming an interconnect layer connecting the gate electrode and the shield electrode.

2. The method of claim 1 wherein the shield electrode and the gate electrode are formed so that both the shield electrode and gate electrode extend out of the trench and over a mesa region, the method further comprising:

forming a plurality of contact openings in the gate electrode so as to expose surface areas of the shield electrode through the contact openings, wherein the interconnect layer fills the contact openings thereby electrically connecting the shield and gate electrode to one another.

3. The method of claim 2 wherein the mesa region is in a non-active region of a die housing the FET.

4. The method of claim 1 wherein the dielectric layer is formed by oxidation of silicon.

5. The method of claim 1 wherein the semiconductor region comprises an epitaxial layer of the first conductivity type over a substrate of the first conductivity type, the method further comprising:

forming a body region of a second conductivity type in the epitaxial layer;

forming source regions of the first conductivity type in the body region adjacent the trench; and

forming heavy body regions of the second conductivity type in the body region adjacent the source regions.

6. The method of claim 1 further comprising forming one or more openings in a portion of the dielectric layer extending over the shield electrode prior to forming the gate electrode so that upon forming the gate electrode in the trench, the gate electrode electrically contacts the shield electrode through the one or more openings.

7. A method of forming a field effect transistor (FET) in a semiconductor die comprising an active region and a non-active region, the method comprising:

forming a plurality of trenches in the active region of the die, the plurality of trenches extending into a semiconductor region;

forming a first polysilicon layer filling each trench and extending over a mesa region in the non-active region of the die.

recessing the first polysilicon layer into each trench so as to form a shield electrode in a bottom portion of each trench, the shield electrode in each trench maintaining continuity with those portions of the first polysilicon layer extending into the mesa region;

forming a dielectric layer by oxidation of silicon such that the dielectric layer lines;

(i) exposed upper sidewalls of each trench, (ii) an upper surface of each shield electrode, and (iii) a surface area of the first polysilicon layer in the mesa region;

forming a second polysilicon layer filling each trench and extending over the dielectric layer in the mesa region;

recessing the second polysilicon layer into each trench so as to form a gate electrode in an upper portion of each trench, the gate electrode in each trench maintaining continuity with those portions of the second polysilicon layer extending into the mesa region;

forming one or more contact openings in those portions of the second polysilicon layer and the dielectric layer extending into the mesa region so as to expose a surface area of the first polysilicon layer through the contact openings; and

forming a gate interconnect layer filling the one or more contact openings to thereby electrically contact the first and second polysilicon layers together.

8. The method of claim 7 further comprising:

prior to forming the first polysilicon layer, forming a shield dielectric layer lining sidewalls and bottom of each trench and extending over the mesa region; and

after recessing the first polysilicon layer into each trench, recessing the shield dielectric layer in each trench so as to expose upper sidewalls of each trench.

9. The method of claim 7 wherein the semiconductor region comprises an epitaxial layer of a first conductivity type over a substrate of the first conductivity type, the method further comprising:

forming a body region of a second conductivity type in the epitaxial layer;

forming source regions of the first conductivity type in the body region adjacent each trench; and

forming heavy body regions of the second conductivity type in the body region adjacent the source regions.

10. A method of forming a field effect transistor (FET), comprising:

forming a plurality of trenches extending into a semiconductor region;

forming a shield electrode in a bottom portion of each trench;

forming a gate electrode in an upper portion of each trench over the shield electrode; and

forming a gate interconnect layer electrically connecting the shield electrode and the gate electrode.