Memory cell array and method of manufacturing the same

• US 7,473,952 B2
• Filed: 05/02/2005
• Issued: 01/06/2009
• Est. Priority Date: 05/02/2005
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Manger, Dirk, Tegen, Stefan, Muemmler, Klaus, Slesazeck, Stefan, Sieck, Alexander
• Primary Examiner(s): Huynh; Andy
• Assistant Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US11/118,768
• Publication Number:
  US 20060244024A1
• Time in Patent Office: 1,345 Days
• Field of Search: None
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Claims

1. An integrated circuit comprising:

a plurality of active areas formed in a semiconductor substrate with a substrate surface, each active area having two lateral sides extending along a first direction with rows of active areas being separated from each other by isolation grooves, wherein each active area includes a first source/drain region formed adjacent the substrate surface, a second source/drain region formed adjacent the substrate surface, and a channel region separating the first and second source/drain regions, each of the first and second source/drain regions being distanced from and oriented with respect to each other along the first direction; and

gate electrodes disposed along the channel regions and being electrically isolated from the channel regions by gate isolating layers; and

a plurality of sets of first and second word lines disposed on opposing lateral sides of each of the rows of active areas and with each of the first and second word lines including a length that extends along the first direction, wherein the first and second word lines of each set are connected with each other via the gate electrodes of a corresponding row of active areas.

2. The integrated circuit according to claim 1, wherein each of the gate electrodes has a top side, the top side of the gate electrode being disposed beneath the surface of the semiconductor substrate.

3. The integrated circuit according to claim 1, wherein each channel region includes a fin-region in which the channel region has the shape of a ridge, the ridge includes a top side and two lateral sides in a cross section perpendicular to a line connecting the first and second source/drain regions, and wherein the gate electrode is disposed at three sides of the ridge.

4. The integrated circuit according to claim 2, wherein each channel region includes a fin-region in which the channel region has the shape of a ridge, the ridge includes a top side and two lateral sides in a cross section perpendicular to a line connecting the first and second source/drain regions, and wherein the gate electrode is disposed at three sides of the ridge.

5. The integrated circuit according to claim 1, wherein two word lines are disposed in each of the isolation grooves, the two word lines being isolated from each other and being assigned to two different rows of active areas.

6. The integrated circuit according to claim 1, further comprising a storage capacitor connected with a first source/drain region, wherein the storage capacitor is a stacked capacitor.

7. The integrated circuit according to claim 1, further comprising a plurality of memory cells, each memory cell comprising a storage capacitor, wherein an active area, a gate electrode, and the memory cells are arranged in rows and columns, respectively, and the memory cells are further arranged in the form of a regular grid.

8. The integrated circuit according to claim 1, wherein each gate electrode has a bottom side, each of the first and second source/drain regions extending to a depth below or equal to the bottom side of the gate electrode.

9. The integrated circuit according to claim 3, wherein each of the first and second source/drain regions extend to a depth below or equal to the top side of the ridge.

10. The integrated circuit according to claim 4, wherein each of the first and second source/drain regions extend to a depth below or equal to the top side of the ridge.

11. The integrated circuit according to claim 1, further comprising:

bit lines extending along a second direction intersecting the first direction, each of the second source/drain regions being connected with one bit line, wherein the bit lines are formed on the substrate surface to be in contact with a plurality of second source/drain regions.

12. The integrated circuit according to claim 1, wherein an isolating spacer is disposed between each first source/drain region and corresponding gate electrode and between each second source/drain region and corresponding gate electrode, the isolating spacer having a larger thickness than the gate isolating layer for each gate electrode.

13. The integrated circuit according to claim 12, wherein each isolating spacer is made of silicon dioxide.

14. The integrated circuit according to claim 1, wherein each of the active areas of one row of active areas are isolated from each other by isolation trenches filled with an isolating material.

15. The integrated circuit according to claim 6, wherein the storage capacitor comprises a storage electrode and a counter electrode, and the storage and counter electrodes are disposed above the substrate surface.

16. The integrated circuit according to claim 11, wherein the bitlines are in direct contact with the second source/drain regions such that no bitline contact is disposed between the bitlines and the second source/drain regions.

17. The integrated circuit according to claim 11, further comprising a storage capacitor is disposed above the bitlines.

18. An integrated circuit including a memory cell array, the memory cell array comprising:

a plurality of memory cells, each of the memory cells including a transistor with a first source/drain region and a second source/drain region, wherein the first and second source/drain regions are distanced from and oriented with respect to each other along a first direction; and

a plurality of word lines, wherein each of the word lines includes a length that extends in the first direction, and wherein each transistor comprises a gate electrode configured to connect with two adjacent word lines.

19. The integrated circuit according to claim 18, further comprising:

active areas arranged in rows, wherein the transistors are formed in the active areas; and

a plurality of isolation grooves, each isolation groove comprising two word lines;

wherein adjacent rows of active areas are separated from each other by the isolation grooves.

20. The integrated circuit according to claim 18, further comprising bitlines extending along a second direction intersecting the first direction.

21. The integrated circuit according to claim 20, wherein the bitlines are in contact with a substrate surface such that no bitline contact is disposed between the bitlines and a source/drain region of a corresponding transistor.

22. The integrated circuit according to claim 21, wherein a storage capacitor is disposed above the bitlines.

23. The integrated circuit according to claim 18, further comprising:

a plurality of bitlines; and

a plurality of storage capacitors disposed above the bitlines.