Fabricated cylinder capacitor for a digital-to-analog converter

• US 7,473,955 B1
• Filed: 03/07/2006
• Issued: 01/06/2009
• Est. Priority Date: 03/07/2006
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Alvand Technologies, Inc. (Renesas Electronics Corporation)
• Inventors: Heshami, Mehrdad, Keramat, Mansour
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): Tran; Tan N
• Application Number:
  US11/371,148
• Time in Patent Office: 1,036 Days
• Field of Search: 257/296, 257/298, 257/300, 257/303, 257/306, 257/307, 257/308, 341/150
• US Class Current: 257/307
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Claims

1. A capacitor device array comprising:

at least two capacitor devices, each capacitor device comprising;

at least two lower layers, each lower layer comprising a bottom plate portion surrounding a top plate portion, the bottom and top plate portions being separated by a distance;

a top layer comprising a top plate portion between two separate bottom plate portions, the two separate bottom plate portions being unconnected across the top layer;

a first set of vias connecting the bottom plate portions of the layers; and

a second set of vias connecting the top plate portions of the layers,

wherein the top plate portions and the second set of vias comprise a top plate of the capacitor device; and

a set of connectors connecting the top plates of the at least two capacitor devices by connecting the top plate portions of the top layers of the at least two capacitor devices.

2. The capacitor device array of claim 1, wherein the capacitor device array is used in a capacitive digital-to-analog converter (DAC).

3. The capacitor device array of claim 2, wherein:

the capacitive DAC has a resolution of a predetermined number of bits, from a least significant bit (LSB) to a most significant bit (MSB); and

the capacitor devices are arranged in a two dimensional array having a predetermined number of columns and rows, the predetermined number of columns and rows being dependent on the resolution of the capacitive DAC.

4. The capacitor device array of claim 3, wherein the architecture of the DAC is a segmented architecture.

5. The capacitor device array of claim 3, wherein:

the architecture of the DAC is a binary weighted architecture;

the at least two capacitor devices have approximately equal capacitance values;

a single capacitor device is coupled to the DAC for the LSB; and

two capacitor devices are coupled to each other and coupled to the DAC for the next LSB.

6. The capacitor device array of claim 1, wherein the capacitor device array is used in a capacitive DAC that is used in a successive approximation analog-to-digital converter (SAR ADC).

7. The capacitor device array of claim 1, wherein the bottom plate portion of each lower layer comprises a single unified structure.

8. A capacitive digital-to-analog converter (DAC) comprising:

a capacitor device array comprising at least two capacitor devices, each capacitor device comprising;

at least two lower layers, each lower layer comprising a bottom plate portion surrounding a top plate portion, the bottom and top plate portions being separated by a distance;

a top layer comprising a top plate portion between two separate bottom plate portions, the two separate bottom plate portions being unconnected across the top layer;

a first set of vias connecting the bottom plate portions of the layers; and

a second set of vias connecting the top plate portions of the layers, wherein the top plate portions and the second set of vias comprise a top plate of the capacitor device; and

a set of connectors connecting the top plates of the at least two capacitor devices by connecting the top plate portions of the top layers of the at least two capacitor devices; and

one or more processing circuits coupled to the capacitor device array for converting a digital code into an analog signal using the capacitor device array.

9. The capacitive DAC of claim 8, wherein:

the capacitive DAC has a resolution of a predetermined number of bits, from a least significant bit (LSB) to a most significant bit (MSB); and

the capacitor devices are arranged in a two dimensional array having a predetermined number of columns and rows, the predetermined number of columns and rows being dependent on the resolution of the capacitive DAC.

10. The capacitive DAC of claim 9, wherein the architecture of the DAC is a segmented architecture.

11. The capacitive DAC of claim 9, wherein:

the architecture of the DAC is a binary weighted architecture;

the at least two capacitor devices have approximately equal capacitance values;

a single capacitor device is used for the LSB; and

two capacitor devices are coupled to each other and used for the next LSB.

12. The capacitive DAC of claim 8, wherein the capacitive DAC is used in a successive approximation analog-to-digital converter (SAR ADC).

13. The capacitive DAC of claim 8, wherein the at least three capacitor devices are arranged in a two dimensional array having at least one column and at least one row and the two dimensional array having at least one column and at least one row is an array having an equal number of columns and rows.

14. The capacitor device array of claim 8, wherein the bottom plate portion of each lower layer comprises a single unified structure.