High density contact to relaxed geometry layers

• US 7,474,000 B2
• Filed: 12/05/2003
• Issued: 01/06/2009
• Est. Priority Date: 12/05/2003
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Petti, Christopher J, Scheuerlein, Roy E
• Primary Examiner(s): Toledo; Fernando L
• Application Number:
  US10/728,451
• Publication Number:
  US 20050127519A1
• Time in Patent Office: 1,859 Days
• Field of Search: 257/758, 257/776, 438/637, 438/668, 438/672, 438/675
• US Class Current: 257/758
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention provides for a via and staggered routing level structure. Vertically overlapping vias connect to two or more routing levels formed at different heights. The routing levels are either both formed above or both formed below the vias, and all are formed above a semiconductor substrate wafer. In this way vias can be formed having a pitch smaller than the pitch of either the first routing level or the second routing level, saving space.

Claims

1. A structure for providing multilevel electrical connectivity within an integrated circuit, the structure comprising:

a first plurality of vias, each having a top end and a bottom end;

a second plurality of vias, each having a top end and a bottom end, wherein the first and second pluralities of vias are vertically overlapping;

a first routing level at a first height, said first level connected to the first plurality of vias at the bottom end of each first via; and

a second routing level at a second height, said second level connected to the second plurality of vias at the bottom end of each second via, wherein the first height is different from the second height,

wherein both routing levels are formed above a substrate,

wherein the first and second vias are evenly spaced and have a common first pitch,

and further comprising a third routing level, the third routing level above the first and second vias connected at the top end of each first and second via,

vertically opposite the first and second routing levels,

wherein the third routing level comprises memory lines in a memory array, and wherein the first plurality of vias are not connected to any routing level above the first routing level and below the third routing level, and wherein the second plurality of vias are not connected to any routing level above the second routing level and below the third routing level.

2. The structure of claim 1 wherein memory cells accessed by the memory lines are charge storage memory cells.

3. The structure of claim 2 wherein the memory cells are SONOS devices.

4. The structure of claim 2 wherein the memory cells are floating gate devices.

5. The structure of claim 2 wherein the memory cells are arranged in a NAND string.

6. The structure of claim 1 wherein memory cells accessed by the memory lines are passive element memory cells.

7. The structure of claim 6 wherein at least one passive element memory cell comprises an antifuse.

8. The structure of claim 6 wherein at least one passive element memory cell comprises a fuse.

9. The structure of claim 1 wherein the memory array is a monolithic three dimensional memory array.

10. The structure of claim 1 wherein the array is a monolithic three dimensional memory array comprising at least first and second memory levels, the second memory level formed vertically above the first memory level.

46. The structure of claim 1 wherein the memory lines have a fourth pitch smaller than the first pitch.

11. A structure for providing multilevel electrical connectivity within an integrated circuit, the structure comprising:

a first plurality of vias, each having a top end and a bottom end;

a second plurality of vias, each having a top end and a bottom end, wherein the first and second pluralities of vias are vertically overlapping;

a first routing level at a first height, said first level connected to the first plurality of vias at the bottom end of each first via;

a second routing level at a second height, said second level connected to the second plurality of vias at the bottom end of each second via, wherein the first height is different from the second height; and

a third routing level at a third height, the third level connected to the first plurality of vias and to the second plurality of vias at the top end of each first and second via, wherein all three routing levels are formed above a substrate,

wherein the first and second vias are evenly spaced and have a first pitch, wherein the third routing level comprises memory lines in a memory array, and

wherein the first plurality of vias are not connected to any routing level above the first routing level and below the third routing level, and wherein the second plurality of vias are not connected to any routing level above the second routing level and below the third routing level.

12. The structure of claim 11 wherein the first routing level has a second pitch, the second routing level has a third pitch, the first pitch smaller than the second pitch and the third pitch.

13. The structure of claim 12 wherein memory cells accessed by the memory lines are charge storage memory cells.

14. The structure of claim 13 wherein the memory cells are SONOS devices.

15. The structure of claim 13 wherein the memory cells are floating gate devices.

16. The structure of claim 13 wherein the memory cells are arranged in a NAND string.

17. The structure of claim 12 wherein memory cells accessed by the memory lines are passive element memory cells.

18. The structure of claim 17 wherein at least one passive element memory cell comprises an antifuse.

19. The structure of claim 17 wherein at least one passive element memory cell comprises a fuse.

20. The structure of claim 11 wherein the memory array is a monolithic three dimensional memory array.

21. The structure of claim 11 wherein the memory lines have a fourth pitch smaller than the first pitch.

22. A structure for providing multilevel electrical connectivity within a memory array, the structure comprising:

a first plurality of vias, each having a top end and a bottom end;

a second plurality of vias, each having a top end and a bottom end, wherein the first and second pluralities of vias are vertically overlapping;

a first routing level at a first height, said first level connected to the first plurality of vias at the top end or the bottom end of each first via;

a second routing level at a second height, said second level connected to the second plurality of vias at the top end or bottom end of each second via, wherein the first height is different from the second height; and

a third routing level at a third height, the third level connected to the first plurality of vias and to the second plurality of vias at the top end or the bottom end of each first or second via, vertically opposite the first or second routing level, where all three routing levels are formed above a substrate,

wherein the first and second vias are evenly spaced and have a first pitch, wherein the array is a monolithic three dimensional memory array comprising at least first and second memory levels, the second memory level formed vertically above the first memory level, and

wherein the first plurality of vias are not connected to any routing level vertically between the first routing level and the third routing level, and wherein the second plurality of vias are not connected to any routing level vertically between the second routing level and the third routing level.

23. A structure for providing multilevel electrical connectivity within an integrated circuit, the structure comprising:

a first plurality of vias, each having a top end and a bottom end;

a second plurality of vias, each having a top end and a bottom end;

a first routing level at a first height, said first level connected to the first plurality of vias at the bottom end of each first via;

a second routing level at a second height, said second level connected to the second plurality of vias at the bottom end of each second via, wherein the first height is different from the second height; and

a third routing level at a third height, the third level connected to the first plurality of vias and to the second plurality of vias at the top end of each first and second via, wherein all three routing levels are formed above a substrate,

wherein the first and second vias are evenly spaced and have a first pitch, wherein the third routing level comprises memory lines in a memory array, and

wherein the first plurality of vias are not connected to any routing level above the first routing level and below the third routing level, and wherein the second plurality of vias are not connected to any routing level above the second routing level and below the third routing level.

24. The structure of claim 23 wherein the first routing level has a second pitch, the second routing level has a third pitch, the first pitch smaller than the second pitch and the third pitch.

25. The structure of claim 24 wherein memory cells accessed by the memory lines are charge storage memory cells.

26. The structure of claim 25 wherein the memory cells are SONOS devices.

27. The structure of claim 25 wherein the memory cells are floating gate devices.

28. The structure of claim 25 wherein the memory cells are arranged in a NAND string.

29. The structure of claim 24 wherein memory cells accessed by the memory lines are passive element memory cells.

30. The structure of claim 29 wherein at least one passive element memory cell comprises an antifuse.

31. The structure of claim 29 wherein at least one passive element memory cell comprises a fuse.

32. The structure of claim 23 wherein the memory array is a monolithic three dimensional memory array.

33. The structure of claim 23 wherein the memory lines have a fourth pitch smaller than the first pitch.

34. A structure for providing multilevel electrical connectivity within an integrated circuit, the structure comprising:

a first plurality of vias, each having a top end and a bottom end;

a second plurality of vias, each having a top end and a bottom end;

a first routing level at a first height, said first level connected to the first plurality of vias at the top or bottom end of each first via;

a second routing level at a second height, said second level connected to the second plurality of vias at the top or bottom end of each second via, wherein the first height is different from the second height; and

a third routing level at a third height, the third level connected to the first plurality of vias and to the second plurality of vias at the top or bottom end of each first and second via, vertically opposite the first or second routing level, wherein all three routing levels are formed above a substrate, wherein the first and second vias are evenly spaced and have a first pitch,

wherein the integrated circuit comprises a memory array,

wherein the memory array is monolithic three dimensional memory array comprising at least first and second memory levels, the second memory level formed vertically above the first memory level, and

wherein the first plurality of vias are not connected to any routing level vertically between the first routing level and the third routing level, and wherein the second plurality of vias are not connected to any routing level vertically between the second routing level and the third routing level.

35. A method for forming a via and routing structure for electrically connecting a multilevel array in an integrated circuit, the method comprising:

forming a first routing level;

forming a second routing level above the first routing level;

forming a first plurality of vias connected at bottom ends to the first routing level;

forming a second plurality of vias connected at bottom ends to the second routing level, wherein the first and second pluralities of vias are vertically overlapping,

wherein the multilevel array comprises a row of vias having a first pitch, the row of vias comprising the first plurality of vias and the second plurality of vias,

vias of the first and second pluralities interspersed,

further comprising forming a third routing level above the first and second routing levels, wherein

said third routing level connects to top ends of the first plurality of vias or

said third routing level connects to top ends of the second plurality of vias,

wherein the third routing level comprises memory lines in a memory array, and wherein the first plurality of vias are not connected to any routing level above the first routing level and below the third routing level, and where the second plurality of vias are not connected to any routing level above the second routing level and below the third routing level.

36. The method of claim 35 wherein the first routing level has a second pitch larger than the first pitch.

37. The method of claim 36 wherein the memory lines have a third pitch smaller than the first pitch.

38. The method of claim 35 wherein memory cells accessed by the memory lines are charge storage memory cells.

39. The method of claim 38 wherein the memory cells are SONOS devices.

40. The method of claim 38 wherein the memory cells are floating gate devices.

41. The method of claim 38 wherein the memory cells are arranged in a NAND string.

42. The method of claim 35 wherein the memory array is a monolithic three dimensional memory array.

43. The method of claim 35 wherein memory cells accessed by the memory lines are passive element memory cells.

44. The method of claim 43 wherein at least one passive element memory cell comprises an antifuse.

45. The method of claim 43 wherein at least one passive element memory cell comprises a fuse.