Three dimensional structure memory

• US 7,474,004 B2
• Filed: 12/18/2003
• Issued: 01/06/2009
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Chiu, Tsz
• Application Number:
  US10/741,602
• Publication Number:
  US 20040151043A1
• Time in Patent Office: 1,846 Days
• Field of Search: 257/777, 257/778
• US Class Current: 257/777
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A stacked integrated circuit comprising:

an integrated circuit;

a plurality of thinned substantially flexible integrated circuits, wherein at least one of the plurality of thinned substantially flexible integrated circuits comprises a low stress dielectric layer, further comprising;

a first substantially flexible integrated circuit having a first surface, wherein a plurality of first interconnections are located on the first surface;

a second substantially flexible integrated circuit having a second surface, wherein a plurality of second interconnections are located on the second surface, said first and second surfaces face each other, said plurality of first interconnection and said plurality of second interconnections are substantially aligned with each other, and said plurality of first interconnections and said plurality of second interconnections are electrically coupled together to form a plurality of vertical interconnections, including redundant vertical interconnections; and

a third interconnection electrically coupling the integrated circuit and at least one of the plurality of thinned substantially flexible integrated circuits, wherein the integrated circuit and the plurality of thinned substantially flexible integrated circuits are positioned in a stacked relation to one another, and wherein at least one of the substantially flexible integrated circuits comprises a substrate formed of a single crystal semiconductor.

2. The device of claim 1, wherein the third interconnection electrically coupling the integrated circuit and at least one of the plurality of thinned substantially flexible integrated circuits is a vertical interconnection internal to the stacked integrated circuit.

3. The device of claim 1, wherein at least one of the thinned substantially flexible integrated circuits have a thickness of less than about 50 microns.

4. The device of claim 1, wherein at least one of the thinned substantially flexible integrated circuits have a thickness of less than about 10 microns.

5. The device of claim 1, wherein at least one of the thinned substantially flexible integrated circuits has a different process technology from one of the integrated circuit and other substantially flexible integrated circuits.

6. The device of claim 5, wherein the different process technology is DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric, or Giant Magneto Resistance.

7. The device of claim 1, wherein the integrated circuit and plurality of thinned substantially flexible integrated circuits comprise at least one of active circuit devices and passive circuit devices.

8. The device of claim 1, wherein at least two of the group consisting of first thinned substantially flexible integrated circuit, second thinned substantially flexible integrated circuit, and integrated circuit are logic integrated circuits, wherein a plurality of data bytes are transferred between the logic integrated circuits.

9. The device of claim 1, further comprising at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

10. The device of claim 1, further comprising at least one data function, wherein the data function is audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, EGG, logical to real address translation, graphical processing, or database management processing.

11. The device of claim 1, further comprising:

a plurality of data lines;

a plurality of gate lines;

an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

a controller for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

12. The device of claim 11, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

13. The device of claim 11, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

14. The device of claim 11, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

15. The device of claim 11, wherein testing of the controller portion of the stacked integrated circuit together with testing by the controller of the memory cells achieves functional testing of the controller and memory cells.

16. The device of claim 11, wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the array of memory.

17. The device of claim 11, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

18. The device of claim 11, wherein altering said address assignments comprises preventing the use of at least one defective gate line without replacement, thereby reducing the amount of available memory storage of the array of memory.

19. The apparatus of claim 1, wherein at least one of the interconnections is a wire bond.

20. The apparatus of claim 1, wherein the low stress dielectric comprises at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and a stress of about 5×

10⁸ dynes/cm² or less.

21. The apparatus of claim 1, wherein the stress of the low stress dielectric is tensile.

22. The integrated circuit of claim 1, wherein the at least one of the plurality of thinned substantially flexible integrated circuits that comprises a low stress dielectric layer further comprises an oxide layer adjacent to the low stress dielectric layer.

23. The integrated circuit of claim 22, wherein the at least one of the plurality of thinned substantially flexible integrated circuits further comprises a passivation layer and a substrate layer, wherein the passivation layer is adjacent to the low stress dielectric layer and nonadjacent to the substrate layer.

24. The integrated circuit of claim 1, wherein said first interconnection comprises a first conductive member protruding through at least a portion of said first substantially flexible integrated circuit, wherein said dielectric layer encapsulates only a portion of said first conductive member.

25. The integrated circuit of claim 1, wherein:

said first interconnection comprises a first conductive member protruding through at least a portion of said first substantially flexible integrated circuit; and

said at least one thinned substantially flexible integrated circuit further comprises a passivation layer, wherein the passivation layer encapsulates only a portion of said first conductive member.

26. A stacked integrated circuit comprising:

a plurality of thinned substantially flexible integrated circuits positioned in a stacked relation to one another, wherein at least one of the plurality of thinned substantially flexible integrated circuits comprises a low stress dielectric layer;

a plurality of first interconnections on a first surface of one of the plurality of thinned substantially flexible integrated circuits; and

a plurality of second interconnections on a second surface of another one of the plurality of thinned substantially flexible integrated circuits, wherein the first and second surfaces face each other, the plurality of first interconnections and plurality of second interconnections are substantially aligned with each other, and the plurality of first interconnection and plurality of second interconnections are electrically coupled together to form a plurality of vertical interconnections, including redundant vertical interconnections, and wherein at least one of the substantially flexible integrated circuits comprises a substrate formed of a single crystal semiconductor.

27. The device of claim 26, wherein the interconnections electrically coupling the thinned substantially flexible integrated circuits are vertical interconnections internal to the stacked integrated circuit.

28. The device of claim 26, wherein at least one of the thinned substantially flexible integrated circuits have a thickness of less than about 50 microns.

29. The device of claim 26, wherein at least one of the thinned substantially flexible integrated circuits have a thickness of less than about 10 microns.

30. The device of claim 26, wherein at least one of the thinned substantially flexible integrated circuits has a different process technology from one of the other substantially flexible integrated circuits.

31. The device of claim 30, wherein the different process technology is DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric, or Giant Magneto Resistance.

32. The device of claim 26, wherein the plurality of thinned substantially flexible integrated circuits comprise at least one of active circuit devices and passive circuit devices.

33. The device of claim 26, wherein at least two of the plurality of thinned substantially flexible integrated circuits are logic integrated circuits, wherein a plurality of data bytes are transferred between the logic integrated circuits.

34. The device of claim 26, further comprising at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

35. The device of claim 26, further comprising at least one data function, wherein the data function is audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing, or database management processing.

36. The device of claim 26, further comprising:

a plurality of data lines;

a plurality of gate lines;

an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

a controller for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

37. The device of claim 36, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

38. The device of claim 36, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

39. The device of claim 36, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

40. The device of claim 36, wherein testing of the controller portion of the stacked integrated circuit together with testing by the controller of the memory cells achieves functional testing of the controller and memory cells.

41. The device of claim 36, wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the array of memory.

42. The device of claim 36, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

43. The device of claim 36, wherein altering said address assignments comprises preventing the use of at least one defective gate line without replacement, thereby reducing the amount of available memory storage of the array of memory.

44. The apparatus of claim 26, wherein at least one of the interconnections is a wire bond.

45. The apparatus of claim 26, wherein the low stress dielectric comprises at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and a stress of about 5×

10⁸ dynes/cm² or less.

46. The apparatus of claim 45, wherein the stress of the low stress dielectric is tensile.

47. The stacked integrated circuit of claim 26, wherein the at least one of the plurality of thinned substantially flexible integrated circuits that comprises a low stress dielectric layer further comprises an oxide layer adjacent to the low stress dielectric layer.

48. The stacked integrated circuit of claim 47, wherein the at least one of the plurality of thinned substantially flexible integrated circuits further comprises a passivation layer and a substrate layer, wherein the passivation layer is adjacent to the low stress dielectric layer and nonadjacent to the substrate layer.

49. The stacked integrated circuit of claim 26, wherein said first interconnection comprises a first conductive member protruding through at least a portion of said one of the plurality of substantially flexible integrated circuits, wherein said dielectric layer encapsulates only a portion of said first conductive member.

50. The stacked integrated circuit of claim 26, wherein:

said first interconnection comprises a first conductive member protruding through at least a portion of said one of the plurality of substantially flexible integrated circuits; and

said one of the plurality of substantially flexible integrated circuits further comprises a passivation layer, wherein the passivation layer encapsulates only a portion of said first conductive member.