Display panel including a plurality of drivers having common wires each for providing reference voltage

• US 7,474,306 B2
• Filed: 10/19/2005
• Issued: 01/06/2009
• Est. Priority Date: 12/16/1999
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Nishi, Kazuyoshi, Doi, Yasuyuki, Oomori, Tetsuro
• Primary Examiner(s): Shalwala; Bipin
• Assistant Examiner(s): Holton; Steven E
• Application Number:
  US11/252,583
• Publication Number:
  US 20060038763A1
• Time in Patent Office: 1,175 Days
• Field of Search: 345/87, 345/204, 345/206, 345/214, 345/55, 345/519
• US Class Current: 345/206
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A source driver 4A arranged on a liquid crystal panel includes therein in-chip reference voltage wires 17 extending from one end to the other end of an LSI chip. The source driver 4A includes therein: branch reference voltage wires 17a branching off from in-chip reference voltage wires 17; reference voltage production buffers 31; a control circuit 30 for controlling the reference voltage production buffers 31; a reference voltage production resistor section 32 for subdividing the reference voltage into values of n steps; voltage level selection circuits 34 each for selecting one of the subdivided voltages; and output buffers 35. Since the reference voltages are supplied to each source driver 4 via wiring for connecting the in-chip reference voltage wires 17 in series with one another, the wiring structure for supplying the reference voltages can be simplified.

Claims

1. A display panel comprising:

a plurality of display elements arranged in a matrix pattern;

a plurality of drivers each for driving a display element of the plurality of display elements, each of the plurality of drivers including;

a plurality of input-side pads, each input-side pad receiving a reference voltage;

a plurality of output-side pads, each output-side pad outputting the reference voltage;

a plurality of in-chip reference voltage wires, each in-chip reference voltage wire directly connecting each input-side pad to each output-side pad to transmit the reference voltage;

a plurality of branch reference voltage wires, each branch reference voltage wire branching off from each in-chip reference voltage wire and transmitting the reference voltage in parallel with each in-chip reference voltage wire;

a plurality of buffers, each buffer coupled to each branch reference voltage wire and outputting an output voltage in response to the reference voltage transmitted by each branch reference voltage wire; and

a selection circuit selecting a voltage for driving the display element in response to output voltages of the plurality of buffers,

a plurality of inter-chip reference voltage wire units, each inter-chip reference voltage wire unit interposed between any two adjacent drivers of the plurality of drivers and including a plurality of inter-chip reference voltage wires, each inter-chip reference voltage wire connecting each output-side pad of one driver of the two adjacent drivers to each input-side pad of the other driver of the two adjacent drivers;

a reference voltage production circuit capable of producing a plurality of reference voltages to drive the plurality of drivers; and

a reference voltage providing wire unit capable of receiving the plurality of reference voltages and providing the plurality of reference voltages to one of the plurality of drivers and including a plurality of reference voltage providing wires, each reference voltage providing wire coupled to each in-chip reference voltage wire via each input-side pad of the one of the plurality of drivers to provide a reference voltage.

2. The display panel of claim 1, each driver of the plurality of drivers further comprising a subdivided voltage production circuit, the subdivided voltage production circuit receiving the output voltages of the plurality of buffers and capable of producing subdivided voltages in response to the output voltages of the plurality of buffers and outputting the subdivided voltages to the selection circuit,

wherein the selection circuit selects one of the subdivided voltages as the voltage for driving the liquid crystal element.

3. The display panel of claim 1, wherein the plurality of buffers include a first buffer receiving a positive-side reference voltage having a higher voltage than a predetermined voltage and a second buffer receiving a negative-side reference voltage having a lower voltage than the predetermined voltage,

each driver of the plurality of drivers further includes:

a positive-side voltage production circuit receiving an output voltage of the first buffer so as to produce positive subdivided voltages and outputting the positive subdivided voltages to the selection circuit; and

a negative-side voltage production circuit receiving an output voltage of the second buffer so as to produce negative subdivided voltages and outputting the negative subdivided voltages to the selection circuit, and

the selection circuit of each driver selects a positive output and a negative output from the positive subdivided voltages and the negative subdivided voltages such that any two adjacent wires each coupled to a display element alternately receive the positive output and the negative output at regular time intervals.

4. The display panel of claim 1, wherein each buffer of the plurality of buffers of each driver of the plurality of drivers has an offset canceling function capable of reducing a potential difference between an input voltage and an output voltage.

5. The display panel of claim 4, wherein each buffer of the plurality of buffers of each driver of the plurality of drivers includes:

an operator capable of receiving an input voltage of the buffer at one terminal and an output voltage of the operator at the other terminal, so as to operate such that the output voltage is substantially equal to the input voltage;

a capacitor including a first electrode and a second electrode and capable of storing a charge corresponding to a voltage difference between the input voltage and the output voltage;

a first node connected to the first electrode of the capacitor;

a second node connected to the second electrode of the capacitor;

a third node for receiving the output voltage from the operator;

a first switching element provided between the second node and the third node;

a second switching element provided between the first node and the one terminal of the operator;

a third switching element provided between the first node and the third node.

6. The display panel of claim 5, each buffer of the plurality of buffers of each driver of the plurality of drivers further comprising a closed circuit added to the second node, the closed circuit including therein a fourth switching element for compensating an electric change in the second node due to the switching of the first switching element.

7. The display panel of claim 4, wherein each buffer of the plurality of buffers of each driver of the plurality of drivers includes two buffering circuits arranged in parallel to each another between an input-side node for receiving an input voltage of each buffer of the plurality of buffers and an output-side node for sending an output voltage of each buffer of the plurality of buffers, each buffering circuit of the two buffering circuits including:

an operator capable of receiving the input voltage of the buffer at one terminal via the input-side node and an output voltage of the operator at the other terminal, so as to operate such that the output voltage of the operator is substantially equal to the input voltage;

a capacitor including a first electrode and a second electrode and capable of storing a charge corresponding to a voltage difference between the input voltage and the output voltage of the operator;

a first node connected to the first electrode of the capacitor;

a second node connected to the second electrode of the capacitor;

a third node for receiving an output voltage from the operator;

a first switching element provided between the second node and the third node;

a second switching element provided between the first node and the input-side node of the operator;

a third switching element provided between the first node and the output-side node; and

a fourth switching element provided between the third node and the output-side node.

8. The display panel of claim 7, each buffering circuit of the two buffering circuits further comprising a closed circuit added to the second node, the closed circuit including therein a fifth switching element for compensating an electric change in the second node due to switching of the first switching element.