Non-volatile memory with both single and multiple level cells
First Claim
1. A memory array, comprising:
- a number of single level non-volatile memory cells;
a number of multiple level non-volatile memory cells;
a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells;
wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells; and
wherein the first single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for an upper page of the first multiple level non-volatile memory cell and a lower resting voltage of the first select gate.
8 Assignments
0 Petitions
Accused Products
Abstract
Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, and operation and their applicability for memory devices and systems. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of single level non-volatile memory cells and a number of multiple level non-volatile memory cells, where a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell.
-
Citations
39 Claims
-
1. A memory array, comprising:
-
a number of single level non-volatile memory cells; a number of multiple level non-volatile memory cells; a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells; wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells; and wherein the first single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for an upper page of the first multiple level non-volatile memory cell and a lower resting voltage of the first select gate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A memory array, comprising:
-
a number of NAND strings of non-volatile memory cells; a number of source select gates on a source side of a string; a number of drain select gates on a drain side of a string; and wherein the number of source select gates includes a number of source select gates individually coupled to a single level non-volatile memory cell, and the number of drain select gates includes a number of drain select gates individually coupled to a single level non-volatile memory cell ; and wherein the single level non-volatile memory cells individually coupled to the source select gates and the single level non-volatile memory cells individually coupled to the drain select gates are coupled to and separated by a continuous series of multiple level non-volatile memory cells ; and wherein the single level non-volatile memory cells have a programmed voltage that is intermediate between a higher programmed voltage for an upper page of the multiple level non-volatile memory cells and a lower resting voltage of the source select gates and the drain select gates. - View Dependent Claims (9, 10, 11, 12)
-
-
13. A memory device, comprising:
-
an array of non-volatile memory cells including a string of non-volatile memory cells; circuitry for control and access to the array of non-volatile memory cells; wherein the array of non-volatile memory cells includes; a number of single level non-volatile memory cells, wherein each single level non-volatile memory cell is only capable of being programmed to two logical states and providing one page of information; a number of multiple level non-volatile memory cells, wherein each multiple level non-volatile memory cell is capable of providing a plurality of pages of information; a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells; wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells; and wherein the first sinale level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for an upper page of the first multiple level non-volatile memory cell and a lower resting voltage of the first select gate. - View Dependent Claims (14, 15, 16)
-
-
17. A memory module, comprising:
-
a number of contacts; two or more memory devices, each having access lines selectively coupled to the number of contacts; and wherein at least one of the memory devices includes; an array of non-volatile memory cells including a string of non-volatile memory cells; circuitry for control and access to the array of non-volatile memory cells; wherein the array of non-volatile memory cells includes; a number of NAND strings of non-volatile memory cells; a number of source select gates on a source side of a string; a number of drain select gates on a drain side of a string; and wherein the number of source select gates includes a number of source select gates individually coupled to a single level non-volatile memory cell, and the number of drain select gates includes a number of drain select gates individually coupled to a single level non-volatile memory cell; and wherein the single level non-volatile memory cells individually coupled to the source select gates and the single level non-volatile memory cells individually coupled to the drain select gates are coupled to and separated by a continuous series of multiple level non-volatile memory cells ; and wherein the single level non-volatile memory cells have a programmed voltage that is intermediate between a higher programmed voltage for an upper page of the multiple level non-volatile memory cells and a lower resting voltage of the source select gates. - View Dependent Claims (18)
-
-
19. An electronic system, comprising:
-
a processor; and a memory device coupled to the processor, wherein the memory device includes; an array of non-volatile memory cells including a NAND string; circuitry for control and access to the array of non-volatile memory cells; and wherein the array of non-volatile memory cells includes; no source select gate and no drain select gate being adjacent a multiple level non-volatile memory cell in the NAND string; each select gate and each drain select gate being adjacent a single level non-volatile memory cell in the NAND string; no multiple level non-volatile memory cell being adjacent more than one single level non-volatile memory cell in the NAND string; and wherein the single level non-volatile memory cells have a programmed voltage that is intermediate between a higher programmed voltage for an upper pane of the adjacent multiple level non-volatile memory cell and a lower resting voltage of the adjacent source select gate or drain select gate. - View Dependent Claims (20)
-
-
21. A method of forming a memory array, comprising:
-
forming a number of series coupled non-volatile memory cells; forming a number of series coupled select gates, wherein the series coupled select gates are coupled in series with the number of non-volatile memory cells; and wherein forming the number of series coupled non-volatile memory cells includes forming a Cast single level non-volatile memory cell directly coupled to a first select gate and directly coupled to a first multiple level non-volatile memory cell; wherein forming the number of series coupled non-volatile memory cells includes forming a second single level non-volatile memory cell directly coupled to a second select gate and directly coupled to a second multiple level non-volatile memory cell; wherein forming the number of series coupled non-volatile memory cells includes forming the first multiple level non-volatile memory cell and the second multiple level non-volatile memory cell directly coupled to at least one interposed multiple level non-volatile memory cell; and wherein forming a single level non-volatile memory cell includes forming a cell that stores a choice of two data input selections equaling one data bit and wherein forming a multiple level non-volatile memory cell includes forming a cell that stores a choice of four data input selections equaling two data bits. - View Dependent Claims (22, 23, 24, 25, 26)
-
-
27. A method of forming a memory block, comprising:
-
adding a number of word lines to a string having a number of single level non-volatile memory cells and a number of multiple level memory cells for maintaining a previous memory block size; wherein of the number of single level non-volatile memory cells are only coupled to an edge word line associated with the string and wherein none of the number of multiple level memory cells are coupled to the edge word line;
andwherein forming a single level non-volatile memory cell includes forming a cell that stores a choice of two data input selections equaling one data bit and wherein forming a multiple level non-volatile memory cell includes forming a cell that stores a choice of four data input selections equaling two data bits. - View Dependent Claims (28, 29, 30, 31)
-
-
32. A method for operating a memory system, comprising:
-
applying a first select line potential to a source select gate and second select line potential to a drain select gate; applying a first word line potential to a second non-volatile memory cell in a NAND string relative to a direction of the source gate and the drain gate that is closer, wherein the second non-volatile memory cell is a first multiple level non-volatile memory cell directly coupled to at least one additional multiple level non-volatile memory cell; and applying a second word line potential to a first non-volatile memory cell in the NAND string, which is a single level non-volatile memory cell, wherein the second word line potential is lower than the first word line potential and greater than a potential of a directly coupled select gate. - View Dependent Claims (33)
-
-
34. A method of programming a memory array, comprising programming a single level memory cell adjacent a select gate to a programmed state, when a next adjacent multiple level memory cell is in a programmed state,
wherein the single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for an upper rage of the next adjacent multiple level non-volatile memory cell and a lower resting voltage of the adjacent select gate.
-
36. A method for programming a NAND flash memory device comprising a memory array having a plurality of source select gates, a plurality of drain select gates, a plurality of single level non-volatile memory cells, and a plurality of multiple level non-volatile memory cells, the method comprising:
-
programming the memory array such that no source select gate and no drain select gate is adjacent a multiple level non-volatile memory cell in a NAND string; programming the memory array such that each source select gate and each drain select gate is adjacent a single level non-volatile memory cell in the NAND string, programming the memory array such that no multiple level non-volatile memory cell is adjacent more than one single level non-volatile memory cell in the NAND string; and wherein the single level non-volatile memory cells have a programmed voltage that is intermediate between a higher programmed voltage for an upper page of an adjacent multiple level non-volatile memory cell and a lower resting voltage of the adjacent source select gate or drain select gate. - View Dependent Claims (37, 38, 39)
-
Specification