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Non-volatile memory with both single and multiple level cells

  • US 7,474,560 B2
  • Filed: 08/21/2006
  • Issued: 01/06/2009
  • Est. Priority Date: 08/21/2006
  • Status: Active Grant
First Claim
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1. A memory array, comprising:

  • a number of single level non-volatile memory cells;

    a number of multiple level non-volatile memory cells;

    a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells;

    wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells; and

    wherein the first single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for an upper page of the first multiple level non-volatile memory cell and a lower resting voltage of the first select gate.

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