Flash / phase-change memory in multi-ring topology using serial-link packet interface
First Claim
1. A multi-ring serial-bus memory system comprising:
- a multi-ring memory controller for generating request packets that contain flash commands, and for receiving completion packets in response to the flash commands;
a first-ring serial link output of the multi-ring memory controller for outputting request packets to a first ring;
a first-ring serial link input of the multi-ring memory controller for receiving completion packets from the first ring in response to request packets sent through the first-ring serial link output;
a first ring of serial flash-memory chips, each serial flash-memory chip in the first ring having a serial input and a serial output and a flash-memory array, wherein the serial output of a prior serial flash-memory chip in the first ring is connected to the serial output of a following serial flash-memory chip in the first ring, and wherein the serial input of an initial serial flash-memory chip in the first ring is connected to the first-ring serial link output, and wherein the serial output of a last serial flash-memory chip in the first ring is connected to the first-ring serial link input;
a second-ring serial link output of the multi-ring memory controller for outputting request packets to a second ring;
a second-ring serial link input of the multi-ring memory controller for receiving completion packets from the second ring in response to request packets sent through the second-ring serial link output;
a second ring of serial flash-memory chips, each serial flash-memory chip in the second ring having a serial input and a serial output and a flash-memory array, wherein the serial output of a prior serial flash-memory chip in the second ring is connected to the serial output of a following serial flash-memory chip in the second ring, and wherein the serial input of an initial serial flash-memory chip in the second ring is connected to the second-ring serial link output, and wherein the serial output of a last serial flash-memory chip in the second ring is connected to the second-ring serial link input; and
a bypassing transceiver in each serial flash-memory chip, the bypassing transceiver comparing a device identifier of a request packet to a current device identifier for the serial flash-memory chip and bypassing and retransmitting the request packet through the serial output when the device identifier mismatches the current device identifier, and decoding the request packet and processing a flash command to generate a completion packet for transmission over the serial output when the device identifier matches the current device identifier,whereby request packets and completion packets are bypassed by serial flash-memory chips in rings connected to the multi-ring memory controller.
1 Assignment
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Accused Products
Abstract
A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.
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Citations
20 Claims
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1. A multi-ring serial-bus memory system comprising:
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a multi-ring memory controller for generating request packets that contain flash commands, and for receiving completion packets in response to the flash commands; a first-ring serial link output of the multi-ring memory controller for outputting request packets to a first ring; a first-ring serial link input of the multi-ring memory controller for receiving completion packets from the first ring in response to request packets sent through the first-ring serial link output; a first ring of serial flash-memory chips, each serial flash-memory chip in the first ring having a serial input and a serial output and a flash-memory array, wherein the serial output of a prior serial flash-memory chip in the first ring is connected to the serial output of a following serial flash-memory chip in the first ring, and wherein the serial input of an initial serial flash-memory chip in the first ring is connected to the first-ring serial link output, and wherein the serial output of a last serial flash-memory chip in the first ring is connected to the first-ring serial link input; a second-ring serial link output of the multi-ring memory controller for outputting request packets to a second ring; a second-ring serial link input of the multi-ring memory controller for receiving completion packets from the second ring in response to request packets sent through the second-ring serial link output; a second ring of serial flash-memory chips, each serial flash-memory chip in the second ring having a serial input and a serial output and a flash-memory array, wherein the serial output of a prior serial flash-memory chip in the second ring is connected to the serial output of a following serial flash-memory chip in the second ring, and wherein the serial input of an initial serial flash-memory chip in the second ring is connected to the second-ring serial link output, and wherein the serial output of a last serial flash-memory chip in the second ring is connected to the second-ring serial link input; and a bypassing transceiver in each serial flash-memory chip, the bypassing transceiver comparing a device identifier of a request packet to a current device identifier for the serial flash-memory chip and bypassing and retransmitting the request packet through the serial output when the device identifier mismatches the current device identifier, and decoding the request packet and processing a flash command to generate a completion packet for transmission over the serial output when the device identifier matches the current device identifier, whereby request packets and completion packets are bypassed by serial flash-memory chips in rings connected to the multi-ring memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A serial-ring non-volatile memory sub-system comprising:
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a serial-ring memory controller means for generating request packets that contain non-volatile-memory commands, and for receiving completion packets in response to the non-volatile-memory commands; wherein the serial-ring memory controller means further comprises a first-ring serial link output means for outputting request packets to a first ring and a first-ring serial link input means for receiving completion packets from the first ring in response to the request packets sent through the first-ring serial link output means; a first ring of serial non-volatile memory devices, each serial non-volatile memory device in the first ring having a serial input and a serial output and a non-volatile-memory array, wherein the serial output of a prior serial non-volatile memory device in the first ring is connected to the serial output of a following serial non-volatile memory device in the first ring, and wherein the serial input of an initial serial non-volatile memory device in the first ring is connected to the first-ring serial link output means, and wherein the serial output of a last serial non-volatile memory device in the first ring is connected to the first-ring serial link input means; and bypassing transceiver means, in each serial non-volatile memory device, for comparing a device identifier of a request packet to a current device identifier for the serial non-volatile memory device and bypassing and retransmitting the request packet through the serial output when the device identifier mismatches the current device identifier, and for decoding the request packet and processing a non-volatile-memory command to generate a completion packet for transmission over the serial output when the device identifier matches the current device identifier, whereby the first ring of serial non-volatile memory devices is controlled by the serial-ring memory controller means. - View Dependent Claims (16, 17, 18, 19)
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20. A Peripheral Component Interconnect (PCI) Express flash-memory serial-ring system comprising:
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a multi-ring memory controller for generating request packets that contain flash commands, and for receiving completion packets in response to the flash commands; a first-ring serial link output of the multi-ring memory controller for outputting request packets to a first ring; a first-ring serial link input of the multi-ring memory controller for receiving completion packets from the first ring in response to request packets sent through the first-ring serial link output; a first ring of serial flash-memory chips, each serial flash-memory chip in the first ring having a serial input and a serial output and a flash-memory array, wherein the serial output of a prior serial flash-memory chip in the first ring is connected to the serial output of a following serial flash-memory chip in the first ring, and wherein the serial input of an initial serial flash-memory chip in the first ring is connected to the first-ring serial link output, and wherein the serial output of a last serial flash-memory chip in the first ring is connected to the first-ring serial link input; a second-ring serial link output of the multi-ring memory controller for outputting request packets to a second ring; a second-ring serial link input of the multi-ring memory controller for receiving completion packets from the second ring in response to request packets sent through the second-ring serial link output; a second ring of serial flash-memory chips, each serial flash-memory chip in the second ring having a serial input and a serial output and a flash-memory array, wherein the serial output of a prior serial flash-memory chip in the second ring is connected to the serial output of a following serial flash-memory chip in the second ring, and wherein the serial input of an initial serial flash-memory chip in the second ring is connected to the second-ring serial link output, and wherein the serial output of a last serial flash-memory chip in the second ring is connected to the second-ring serial link input; a bypassing transceiver in each serial flash-memory chip, the bypassing transceiver comparing a device identifier of a request packet to a current device identifier for the serial flash-memory chip and bypassing and retransmitting the request packet through the serial output when the device identifier mismatches the current device identifier, and decoding the request packet and processing the flash command to generate a completion packet for transmission over the serial output when the device identifier matches the current device identifier, wherein each serial flash-memory chip comprises; a flash memory array of non-volatile electrically-erasable programmable read-only memory (EEPROM) cells; address decoders, receiving a flash address, the address decoders selecting a subset of the EEPROM cells for reading, writing, or erasing; a high-voltage generator for generating elevated voltages above a power-supply voltage for programming and erasing the EEPROM cells; data buffers for storing data being written to the EEPROM cells; a command register receiving a non-volatile-memory command; control logic, responsive to the non-volatile-memory command in the command register, for controlling reading, writing, and erasing of the EEPROM cells; a serial interface to external pins of the PCI Express flash-memory chip that connect to the serial input and to the serial output that are externally connected to different external devices, the serial interface having a physical layer; wherein the serial input connects to half of a PCI Express serial bus having differential data lines that carry data serially; wherein the serial output connects to half of a PCI Express serial bus having differential data lines that carry data serially; a controller, connected between the serial interface and the command register and data buffers, the controller comprising; a data-link layer that encapsulates transaction-layer packets for transmission over the serial output after framing by the physical layer; a transaction layer that generates headers to attach to data payloads to generate the transaction-layer packets; read operation means, responsive to a memory-read-request packet received by the serial input having a header with the flash address, for sending a read command to the command register and sending the flash address to the address decoders, and transferring data read from the EEPROM cells from the data buffers to the transaction layer as a data payload, the transaction layer attaching the data payload to a header to generate a completion packet with the read data, the completion packet being sent over the serial output as a response to the memory-read-request packet; program operation means, responsive to a memory-write-request packet received over the serial input having a header with the flash address, for sending a write command to the command register and sending the flash address to the address decoders, and transferring data write from a data payload of the memory-write-request packet to the data buffers for writing to the EEPROM cells; erase operation means, responsive to a message packet received over the serial input having a header with an erase indicator, for sending an erase command to the command register, and generating a message packet for transmission over the serial output once the EEPROM cells have been erased; and reset operation means, responsive to a message packet received over the serial input having a header with a reset indicator, for sending a reset command to the control logic to reset the control logic and to reset the controller, whereby operations indicated by commands in serial packets received over the serial input are executed and data is returned in data payloads of serial packets.
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Specification