Methods for forming shielded gate field effect transistors

• US 7,476,589 B2
• Filed: 06/29/2006
• Issued: 01/13/2009
• Est. Priority Date: 06/29/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kraft, Nathan Lawrence, Grebs, Thomas E., Ridley, Rodney
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Ahmadi; Mohsen
• Application Number:
  US11/479,117
• Publication Number:
  US 20070032020A1
• Time in Patent Office: 929 Days
• Field of Search: 257/E21.158, 257/E21.4, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.

Claims

1. A method for forming a field effect transistor comprising:

forming a trench in a semiconductor region;

forming a dielectric layer lining the trench sidewalls and bottom;

filling the trench with a conductive material;

recessing the conductive material into the trench to thereby form a shield electrode in a bottom portion of the trench;

after the recessing step, removing exposed portions of the dielectric layer whereby the dielectric layer is recessed in the trench to below a top surface of the shield electrode;

recessing the shield electrode so that a top surface of the recessed shield electrode is substantially coplanar with a top surface of the recessed dielectric layer; and

forming an inter-electrode dielectric (IED) over the recessed shield electrode.

2. The method of claim 1 wherein the recessing comprises:

isotropic etching of the conductive material.

3. The method of claim 2 wherein the recessing comprises:

prior to isotropic etching, anisotropic etching of the conductive material.

4. The method of claim 2 wherein the recessing comprises:

prior to the isotropic etching, an isotropic etching of the conductive material; and

after the isotropic etching, anisotropic etching of the conductive material.

5. The method of claim 2 wherein the recessing comprises:

after the isotropic etching, an isotropic etching of the conductive material; and

after the anisotropic etching, isotropic etching of the conductive material.

6. The method of claim 1 further comprising forming a gate electrode in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED.

7. The method of claim 6 wherein the semiconductor region has a first conductivity type, the method further comprising:

forming a body region of a second conductivity type in the semiconductor region; and

forming source regions of the first conductivity type in the body region flanking the trench.

8. The method of claim 7 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and die french is formed so as to extend through the epitaxial layer and terminate within the substrate.

9. The method of claim 7 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend into and terminate within the epitaxial layer.

10. A method for forming a field effect transistor comprising:

forming a trench in a semiconductor region;

forming a dielectric layer lining the trench sidewalls and bottom;

filling the trench with a conductive material;

recessing the conductive material into the trench to thereby form a shield electrode in a bottom portion of the trench;

after the recessing step, removing exposed portions of the dielectric layer whereby the dielectric layer is recessed in the trench to below a top surface of the shield electrode;

recessing the shield electrode to below a top surface of the recessed dielectric layer; and

forming an inter-electrode dielectric (IED) over the recessed shield electrode.

11. The method of claim 10 wherein the recessing comprises:

isotropic etching of the conductive material.

12. The method of claim 11 wherein the recessing comprises:

prior to isotropic etching, anisotropic etching of the conductive material.

13. The method of claim 11 wherein the recessing comprises:

prior to the isotropic etching, anisotropic etching of the conductive material; and

after the isotropic etching, anisotropic etching of the conductive material.

14. The method of claim 11 wherein the recessing comprises:

after the isotropic etching, anisotropic etching of the conductive material; and

after the anisotropic etching, isotropic etching of the conductive material.

15. The method of claim 10 further comprising forming a gate electrode in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED.

16. The method of claim 15 wherein the semiconductor region has a first conductivity type, the method further comprising:

forming a body region of a second conductivity type in the semiconductor region; and

forming source regions of the first conductivity type in the body region flankling the trench.

17. The method of claim 16 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend through the epitaxial layer and terminate within the substrate.

18. The method of claim 16 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend into and terminate within the epitaxial layer.