6F2 access transistor arrangement and semiconductor memory device
First Claim
1. An integrated circuit, comprising:
- a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor, each access transistor comprising a gate electrode and an active area, each active area being formed in a substrate and adjacent to a pattern surface of the substrate, each gate electrode being disposed at least in part in a recess groove that is formed in the active area between a respective node contact section and a respective bit line contact section formed within the respective active area, the third access transistor being arranged adjacent to the second access transistor such that the bit line contact sections of the second and third access transistors form a common bit line contact section and such that the active areas of the second and third access transistors form a contiguous semiconductor line;
an isolation transistor arranged between the first and the second access transistors, the first and the second access transistors facing laterally reversed and opposing the isolation transistor, the node contact sections of the first and second access transistors being adjacent to the isolation transistor; and
a further isolation transistor arranged between the third and the fourth access transistors, the third and fourth access transistors facing laterally reversed and opposing the further isolation transistor, the node contact sections of the third and fourth access transistors being adjacent to the further isolation transistor;
wherein the isolation transistors are controllable by isolation gate lines, each isolation gate line being disposed at least in part in an isolation groove and being separated from the substrate by an isolation gate dielectric, the isolation groove being formed in the substrate between the node contact sections of the first and the second access transistors and between the node contact sections of the third and the fourth access transistors.
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Accused Products
Abstract
An access transistor arrangement is provided for a 6F2 stacked capacitor DRAM memory cell layout with shared bit line contacts. The access transistors are arranged in pairs along semiconductor lines. The two transistors of each pair of transistors are arranged laterally reversed opposing the respective common bit line section. Each pair of access transistors is separated from the adjacent pair of access transistors by an isolation transistor which is permanently turned off. The access transistors and the isolation transistors are formed as identical recessed channel transistors with elongated channel and enhanced isolation properties. The same dopant concentration may be provided for both junctions of the access transistors. As identical devices are provided both as access transistor and as isolation transistors, the complexity of lithographic patterning processes is reduced.
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Citations
17 Claims
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1. An integrated circuit, comprising:
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a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor, each access transistor comprising a gate electrode and an active area, each active area being formed in a substrate and adjacent to a pattern surface of the substrate, each gate electrode being disposed at least in part in a recess groove that is formed in the active area between a respective node contact section and a respective bit line contact section formed within the respective active area, the third access transistor being arranged adjacent to the second access transistor such that the bit line contact sections of the second and third access transistors form a common bit line contact section and such that the active areas of the second and third access transistors form a contiguous semiconductor line; an isolation transistor arranged between the first and the second access transistors, the first and the second access transistors facing laterally reversed and opposing the isolation transistor, the node contact sections of the first and second access transistors being adjacent to the isolation transistor; and a further isolation transistor arranged between the third and the fourth access transistors, the third and fourth access transistors facing laterally reversed and opposing the further isolation transistor, the node contact sections of the third and fourth access transistors being adjacent to the further isolation transistor; wherein the isolation transistors are controllable by isolation gate lines, each isolation gate line being disposed at least in part in an isolation groove and being separated from the substrate by an isolation gate dielectric, the isolation groove being formed in the substrate between the node contact sections of the first and the second access transistors and between the node contact sections of the third and the fourth access transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 17)
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8. A semiconductor memory device, comprising:
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a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor, each access transistor comprising a gate electrode and an active area, the active area being formed within a semiconductor substrate; each active area comprising a bit line contact section, a node contact section and a channel section, the bit line contact section and the node contact section being adjacent to a pattern surface of the substrate, and the channel section separating the bit line contact section and the node contact section; and each gate electrode being disposed at least in parts in a recess groove formed in the substrate between the respective node contact section and the respective bit line contact section and each gate electrode being separated from the respective channel section by a gate dielectric, the third access transistor being arranged adjacent to the second access transistor such that the bit line contact sections of the second and third access transistors form a common bit line contact section and such that the active areas of the second and third access transistors form a contiguous semiconductor line; the semiconductor memory device further comprising; storage capacitors being disposed above the pattern surface, each storage capacitor being coupled to one of the node contact sections; a bit line, the bit line being coupled to the bit line contact sections; and an isolation transistor being arranged between the first and the second access transistors, the first and the second access transistors facing laterally reversed and opposing the isolation transistor, the node contact sections of the first and second access transistors being adjacent to the isolation transistor; a further isolation transistor arranged between the third and the fourth access transistors, the third and fourth access transistors facing laterally reversed and opposing the further isolation transistor, the node contact sections of the third and fourth access transistors being adjacent to the further isolation transistor; wherein the isolation transistors are controllable by isolation gate lines, each isolation gate line being disposed at least in part in an isolation groove formed in the substrate between the node contact sections of the first and the second access transistors and between the node contact sections of the third and the fourth access transistors and being separated from the substrate by an isolation gate dielectric. - View Dependent Claims (9, 10, 11, 12)
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13. An integrated circuit comprising a semiconductor memory device that comprises:
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a plurality of first access transistors and a plurality of second access transistors, each access transistor having a gate electrode and an active area, the active area being formed within a semiconductor substrate; each active area comprising a bit line contact section, a node contact section and a channel section, the bit line contact section and the node contact section being adjacent to a pattern surface of the substrate and the channel section separating the bit line contact section and the node contact section; and each gate electrode being disposed at least in part in a recess groove formed in the substrate between the respective node contact section and the respective bit line contact section, and each gate electrode being separated from the respective channel section by a gate dielectric; the semiconductor memory device further comprising; a plurality of isolation transistors, each isolation transistor being arranged between a pair of one of the first and one of the second access transistors, the first and the second access transistors facing laterally reversed and opposing the isolation transistor, the node contact section of the first access transistor and the node contact section of the second access transistor being adjacent to the isolation transistor; a plurality of isolation gate lines of the isolation transistors being separated from the substrate by an isolation gate dielectric layers and being disposed at least in parts in isolation grooves, the isolation grooves being formed in the substrate between the node contact sections of the first and the second access transistors; wherein a plurality of the access transistors are arranged in lines such that the bit line contact sections of neighboring first and second access transistors form a common bit line contact section and such that the active areas of the access transistors form a contiguous semiconductor line. - View Dependent Claims (14, 15, 16)
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Specification