U-shape metal-oxide-semiconductor (UMOS) gate structure for high power MOS-based semiconductor devices

• US 7,476,932 B2
• Filed: 09/29/2006
• Issued: 01/13/2009
• Est. Priority Date: 09/29/2006
• Status: Expired due to Fees

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Chang, Hsueh-Rong, Zhang, Qingchun
• Primary Examiner(s): Quach; Tuan N.
• Application Number:
  US11/537,454
• Publication Number:
  US 20080079065A1
• Time in Patent Office: 837 Days
• Field of Search: 257/330, 257/332, 257/E29.26, 257/E21.428, 438/270, 438/272
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A U-shape Metal-Oxide-Semiconductor (UMOS) device comprises a P-base layer, an N+ source region disposed in the P-base layer where the source region has a first surface coplanar with a first surface of the P-base layer, a dielectric layer extending through the P-base layer and forming a U-shape trench having side walls and floor enclosing a trench interior region, a conducting gate material filling the trench interior region, a first accumulation channel layer disposed along a first side wall of the U-shape trench and in contact with the source region and a first side wall of the U-shape trench, a P-junction gate disposed adjacent to the dielectric layer floor and in proximity to the first accumulation channel layer, and an N-drift region where the P-junction gate is disposed between the dielectric layer and the N-drift region.

Claims

1. A U-shape Metal-Oxide-Semiconductor (UMOS) device, comprising:

a P-base layer;

an N+ source region disposed in the P-base layer, the N+ source region having a first surface that is coplanar with a first surface of the P-base layer;

a dielectric layer extending through the P-base layer and forming a U-shape trench having side walls and a floor enclosing a trench interior region;

a conducting gate material filling the U-shape trench interior region;

a first accumulation channel layer disposed along a first side wall of the H-shape trench and in contact with the N+ source region and the first side wall of the U-shape trench;

a P-junction gate disposed adjacent to the dielectric layer floor and in proximity to the first accumulation channel layer;

an N-drift region, wherein the P-junction gate is disposed between the dielectric layer and the N-drift region;

a N+ drain region adjacent to a second wall of the U-shape trench, the second wall being disposed on a side opposite from the first side wall; and

a second accumulation channel layer along the second side wall of the trench and in contact with the N+ drain region.

2. The device of claim 1, wherein the P-base layer is composed of a positively doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC), the P-base layer having a doping concentration of between about 1×

10¹⁶ cm<sup>−

3</sup> and about 5×

10¹⁷ cm<sup>−

3</sup>, the P-base layer having a thickness of between about 1.0 microns and about 2.0 microns.

3. The device of claim 1, wherein the N+ source region is composed of negatively doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC), the source region having a doping concentration of between about 1×

10¹⁸ cm<sup>−

3</sup> and about 1×

10²⁰ cm<sup>−

3</sup>.

4. The device of claim 1, wherein the dielectric layer has a thickness of between about 500 Å

and about 800 Å

, the dielectric layer being composed of a dielectric material selected from the group consisting of silicon dioxide (Si02) and silicon nitride (Si3N4).

5. The device of claim 1, wherein the conducting gate material consists of a positively doped semiconductor material selected from the group consisting of silicon (Si), poly-silicon, and silicon carbide (SiC), the gate material having a doping concentration of between about 5×

10¹⁷ cm<sup>−

3</sup> to about 5×

10¹⁹ cm<sup>−

3</sup>, the gate material having a thickness from about 1.5 microns to about 2.0 microns.

6. The device of claim 1, wherein the first accumulation layer is composed of an N-type doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC), the first accumulation layer having a doping concentration of between about 1×

10¹⁵ cm<sup>−

3</sup> to about 1×

10¹⁷ cm<sup>−

3</sup>, the first accumulation layer having a thickness from about 0.2 microns to about 0.5 microns.

7. The device of claim 1, wherein the P-junction gate is composed of a P-type doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC), the P-junction gate having a doping concentration of between about 5×

10¹⁷ cm<sup>−

3</sup> and 5×

10¹⁸ cm<sup>−

3</sup>, the P junction gate being one of blanket doped and locally doped, the P-junction gate having thickness from about 0.3 microns to about 0.5 microns.

8. The device of claim 1, further comprising a doped buffer layer disposed between the P-base layer and the N-drift region, the dielectric layer extending through the P-base layer and into the doped buffer layer to form the U-shape trench, the doped buffer layer providing an accumulation conducting channel along the first accumulation layer.

9. The device of claim 8, wherein the doped buffer layer comprises a negatively doped semiconductor material having a doping concentration of between about 5×

10¹⁵ cm<sup>−

3</sup> and about 5×

10¹⁶ cm<sup>−

3</sup>, the doped buffer layer having a thickness from about 1.0 microns to about 2.0 microns.

10. The device of claim 9, wherein a first side of the P-junction layer is directly adjacent to the dielectric layer and the remaining sides of the P-junction layer are in contact with the doped buffer layer.

11. The device of claim 1, wherein the N-drift region is composed of a negatively doped semiconductor material having a doping concentration of between about 2×

10¹⁴ cm<sup>−

3</sup> and about 1×

10¹⁷ cm<sup>−

3</sup> , the N-drift region having a thickness from about 5 microns to about 200 microns.

12. The device of claim 1, further comprising a doped substrate, adjacent to the N-drift region, composed of a semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC), the doped substrate including a doped semiconductor material having a doping concentration from between about 1×

10¹⁸ cm<sup>−

3</sup> to about 1×

10¹⁹ cm<sup>−

3</sup>.

13. The device of claim 1, wherein the drain region comprises a negatively doped semiconductor material having a doping concentration from between about 1×

10¹⁸ cm<sup>−

3</sup> to about 5×

10¹⁹ cm<sup>−

3</sup>; and

wherein the second accumulation channel layer comprises a negatively doped semiconductor material having a doping concentration from about 1×

10¹⁵ cm<sup>−

3</sup> to about 1×

10¹⁷ cm<sup>−

3</sup>, the second accumulation channel layer having a thickness from about 0.2 microns to about 0.5 microns.

14. The device of claim 13, further comprising a source terminal in contact with the N+ source region, a gate terminal in contact with the conducting gate material, and a drain terminal in contact with the N+ drain region, the source terminal, gate terminal, and drain terminal being composed of an electrically conductive material selected from the group consisting of aluminum (Al), copper (Cu), and nickel (Ni).

15. A gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device, comprising:

a P-base layer having a first surface and a second surface;

a doped buffer layer having a first surface and a second surface, a portion of the doped buffer layer first surface being adjacent to the P-base second surface;

a dielectric layer extending through the P-base layer and into the doped buffer layer to form a U-shape trench having side walls and a floor enclosing a U-shape trench interior region;

a conducting gate material filling the U-shape trench interior region;

a P-junction gate having a first surface that is adjacent to the trench floor, remaining surfaces of the P-junction gate being in contact with the doped buffer layer;

a N-drift region having a first surface and a second surface, the N-drift region first surface being adjacent to the doped buffer layer second surface;

an N+ source region disposed in the P-base layer, the N+ source region having a first surface that is coplanar with the first surface of the P-base layer;

a first accumulation channel layer disposed along a first side wall of the U-shape trench and in contact with the N+ source region;

a N+ drain region adjacent to a second side wall of the U-shape trench, the second side wall being disposed on a side opposite from the first side wall; and

a second accumulation channel layer disposed along the second side wall of the U-shape trench and in contact with the N+ drain region.

16. The gate structure of claim 15, wherein a distance between the trench floor and the doped buffer layer second surface is sufficient to provide a junction depletion region wholly embedded within the doped buffer layer.

17. The gate structure of claim 15, wherein the dielectric layer has a thickness of between about 500 Å

and about 800 Å

, the dielectric layer being composed of a dielectric material selected from the group consisting of silicon dioxide (SiO2) and silicon nitride (Si3N4).

18. A method of using a UMOS field effect transistor (FET), the UMOS FET comprising:

a P-base layer;

an N+ source region disposed in the P-base layer, the N+ source region having a first surface that is coplanar with a first surface of the P-base layer, the N+ source region having a source terminal in electrical contact with the N+ source region;

a dielectric layer extending through the P-base layer and forming a U-shape trench having side walls and a floor enclosing a trench interior region;

a conducting gate material filling the U-shape trench interior region, the conducting gate material having a gate terminal in electrical contact with the conducting gate material;

a first accumulation channel layer along a first side wall of the U-shape trench and in contact with both the N+ source region and a first side wall of the U-shape trench;

a P-junction gate disposed adjacent to the dielectric layer floor and in proximity to the first accumulation channel layer;

an N-drift region, wherein the P-junction gate is disposed between the dielectric layer and the N-drift region;

a N+ drain region adjacent to a second side wall of the U-shape trench, the second side wall being disposed on a side opposite from the first side wall, the N+ drain region having a drain terminal in electrical contact with the N+ drain region; and

a second accumulation channel layer along the second side wall of the U-shape trench and in contact with the N+ drain region, and

wherein the method of using the UMOS FET comprises;

applying a controlling voltage to the gate terminal, the controlling voltage applied to the UMOS FET being effective in controlling the flow of electrical current through the source terminal and the drain terminal.

19. The method of claim 18, wherein the dielectric layer has a thickness of between about 500 Å

and about 800 Å

, the dielectric layer being composed of a dielectric material selected from the group consisting of silicon dioxide (Si02) and silicon nitride (Si3N4).

20. The method of claim 19, wherein the semiconductor material is selected from the group consisting of silicon (Si) and silicon-carbide (SiC).

21. A method of making a U-shape Metal-oxide-Semiconductor (UM0S) device, comprising:

providing a P-base layer having a first surface and a second surface;

providing a doped buffer layer having a first surface and a second surface, a portion of the doped buffer layer first surface being adjacent to the P-base second surface;

providing a dielectric layer extending through the P-base layer and into the doped buffer layer to form a U-shape trench having side walls and a floor enclosing a U-shape trench interior region;

providing a conducting gate material filling the U-shape trench interior region; and

providing a P-junction gate having a first surface that is adjacent to the trench floor, remaining surfaces of the P-junction gate being in contact with the doped buffer layer,

wherein a distance between the trench floor and the doped buffer layer second surface is sufficient to provide a junction depletion region wholly embedded within the doped buffer layer;

providing an N+ source region disposed in the P-base layer, the N+ source region having a first surface that is coplanar with a first surface of the F-base layer;

providing a first accumulation channel layer along a first side wall of the u-shape trench and in contact with the N+ source region and a first side wall of the U-shape trench,

wherein the doped buffer layer provides an accumulation conducting channel along the first accumulation channel layer;

providing an N+ drain region disposed in the P-base layer, the N+ drain region having a first surface that is coplanar with a first surface of the P-base layer; and

providing a second accumulation channel layer along a second side wall of the U-shape trench and in contact with the N+ drain region and a second side wall of the U-shape trench,

wherein the doped buffer layer provides an accumulation conducting channel along the second accumulation channel layer.

22. The method of claim 21, further comprising:

providing an N-drift region adjacent to the doped buffer layer, wherein the P-junction gate is disposed between the dielectric layer and the N-drift region; and

providing a doped substrate adjacent to the N-drift region on a side opposite from the P-base layer.

23. The method of claim 21, wherein first and second accumulation channel layers are composed of an N-type doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC) and having a doping concentration of between about 1×

10¹⁵ cm<sup>−

3</sup> to about 1×

10¹⁷ cm<sup>−

3</sup> and having a thickness from about 0.2 microns to about 0.5 microns.

24. The method of claim 21, further comprising a source terminal in contact with the N+ source region, a gate terminal in contact with the conducting gate material, and a drain terminal in contact with the N+ drain region, the source terminal, gate terminal, and drain terminal being composed of an electrically conductive material selected from the group consisting of aluminum (Al), copper (Ca), and nickel (Ni).