Vertical gated access transistor

• US 7,476,933 B2
• Filed: 03/02/2006
• Issued: 01/13/2009
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Wilson; Allan R.
• Application Number:
  US11/366,212
• Publication Number:
  US 20070205443A1
• Time in Patent Office: 1,048 Days
• Field of Search: 257/350, 257/500, 257/391, 257/E27.092, 257330-332, 257/E27.091, 257301-303
• US Class Current: 257/331
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked.

Claims

1. An apparatus comprising:

a semiconductor substrate having an array portion and a logic portion;

at least one U-shaped semiconductor structure formed in the substrate array portion, the semiconductor structure comprising a first source/drain region positioned atop a first pillar, a second source/drain region positioned atop a second pillar, and a U-shaped channel connecting the first and second source/drain regions, wherein the U-shaped channel is contiguous with the semiconductor substrate;

an elongated spacer formed adjacent to the U-shaped semiconductor structure, wherein the elongated spacer is formed in an intermediate-depth trench that is deeper than a shallow trench that separates the first pillar from the second pillar, the intermediate-depth trench having a floor defined by the semiconductor substrate;

a deep trench having a floor defined by the semiconductor substrate, the floor of the deep trench being deeper than the floor of the intermediate trench, wherein the deep and shallow trenches are parallel to each other; and

at least one transistor device formed over the substrate logic portion, the transistor device including a gate dielectric layer and a gate material, wherein the gate dielectric layer is elevated with respect to the first and second source/drain regions.

2. The apparatus of claim 1, wherein the at least one transistor device is a planar transistor.

3. The apparatus of claim 1, wherein the first and second source/drain regions further comprise a region of doped semiconductor material.

4. The apparatus of claim 1, wherein a first U-shaped semiconductor structure is separated from a second U-shaped semiconductor structure by the deep trench.

5. The apparatus of claim 4, wherein the deep trench and the shallow trench are filled with an oxide material.

6. The apparatus of claim 1, further comprising a spacer formed adjacent to a vertical sidewall of the at least one transistor device.

7. The apparatus of claim 6, wherein the spacer comprises a nitride material.

8. The apparatus of claim 6, wherein the spacer has a width that is greater than or equal to half of a width of the first pillar.

9. The apparatus of claim 1, wherein the elongated spacer is separated from the U-shaped semiconductor structure by an oxide layer.

10. The apparatus of claim 1, wherein the elongated spacer comprises a conductive gate material.

11. The apparatus of claim 1, wherein the elongated spacer crosses the shallow trench.

12. The apparatus of claim 1, wherein the at least one transistor device does not include an insulating cap layer formed thereover.

13. The apparatus of claim 1, wherein the gate dielectric layer comprises an oxide material.

14. The apparatus of claim 1, wherein the gate material comprises a polycrystalline silicon material.

15. The apparatus of claim 14, wherein the gate material further comprises a metal silicide.

16. The apparatus of claim 15, wherein the metal silicide comprises a material selected from the group consisting of tungsten silicide and titanium silicide.

17. The apparatus of claim 1, further comprising:

a capacitor formed over the first source/drain region; and

an insulated bit line formed over the second source/drain region.

18. A memory device comprising:

a substrate having an array portion and a logic portion;

a plurality of U-shaped semiconductor structures that are formed in the array portion of the substrate, wherein the U-shaped semiconductor structures are defined by a pattern of alternating deep and shallow trenches that are crossed by a pattern of intermediate-depth trenches, and wherein the deep and intermediate trenches have floors defined by the substrate, the deep trenches being deeper than the intermediate trenches when measured from a common reference elevation to the floors of the deep and intermediate trenches;

an elongated spacer formed adjacent to the U-shaped semiconductor structures and in the intermediate-depth trenches; and

a plurality of transistor devices formed over the logic portion of the substrate, wherein the transistor devices include a gate oxide layer, an uncapped gate layer, and a sidewall spacer structure.

19. The memory device of claim 18, wherein the plurality of transistor devices are formed using a photolithographic mask that is also simultaneously used to pattern at least a portion of the plurality of U-shaped semiconductor structures over the array portion of the substrate.

20. The memory device of claim 18, wherein the alternating deep and shallow trenches are filled with an oxide material.

21. The memory device of claim 18, wherein the alternating deep and shallow trenches are filled with a spin-on dielectric material.

22. The memory device of claim 18, wherein the shallow trenches are at least partially filled with a conductive gate material.

23. The memory device of claim 18, wherein the U-shaped semiconductor structures include a channel portion that is contiguous with the substrate array portion.

24. The memory device of claim 18, wherein the substrate comprises single crystal silicon.

25. The memory device of claim 18, wherein the plurality of transistor devices formed over the logic portion of the substrate are planar transistor devices.

26. The memory device of claim 18, wherein the plurality of transistor devices formed over the logic portion of the substrate include a silicide region positioned over the uncapped gate layer.

27. The memory device of claim 26, wherein the silicide region comprises a material selected from the group consisting of tungsten silicide and titanium silicide.