Memory cell having an electrically floating body transistor and programming technique therefor
First Claim
1. An integrated circuit comprising:
- a semiconductor memory cell comprising an electrically floating body transistor comprising;
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and
a gate disposed over the body region and separated therefrom by a gate dielectric; and
wherein the memory cell includes;
a first data state representative of a first charge in the body region; and
a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing carriers from the body region through the gate; and
control circuitry, coupled to the memory cell, to generate control signals, including first control signals, to program one of a plurality of data states into the memory cell, wherein, in response to the first control signals applied to the memory cell, the electrically floating body transistor provides the second charge in the body region by removing carriers from the body region through the gate.
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Accused Products
Abstract
A memory cell comprising an electrically floating body transistor including a source region, a drain region, a body region disposed therebetween, wherein the body region is electrically floating, and a gate disposed over the body region and separated therefrom by a gate dielectric. The memory cell includes a first data state representative of a first charge in the body region and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing carriers from the body region through the gate. Thus, a memory cell may be programmed to a logic low by, for example, causing, forcing and/or inducing carriers in the floating body of the transistor to tunnel through or traverse the gate dielectric to the gate of the electrically floating body transistor (and, in many array configurations, the word line of a memory cell array).
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Citations
26 Claims
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1. An integrated circuit comprising:
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a semiconductor memory cell comprising an electrically floating body transistor comprising; a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region and separated therefrom by a gate dielectric; and wherein the memory cell includes; a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing carriers from the body region through the gate; and control circuitry, coupled to the memory cell, to generate control signals, including first control signals, to program one of a plurality of data states into the memory cell, wherein, in response to the first control signals applied to the memory cell, the electrically floating body transistor provides the second charge in the body region by removing carriers from the body region through the gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 22, 25)
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8. An integrated circuit comprising:
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a semiconductor memory cell array comprising a plurality of dynamic random access memory cells arranged in a matrix of rows and columns, each dynamic random access memory cell comprises a transistor, each transistor comprises; a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region and separated therefrom by a gate dielectric; and wherein each dynamic random access memory cell includes; a first data state representative of a first charge in the body region of the associated transistor; and a second data state representative of a second charge in the body region of the associated transistor wherein the second charge is substantially provided by removing carriers from the body region through the gate of the associated transistor; and control circuitry, coupled to the dynamic random access memory cells, to generate control signals, including first control signals, to program one of a plurality of data states into the memory cells, wherein, in response to first control signals applied to a first plurality of memory cells, the electrically floating body transistor associated with each memory cell of the first plurality of memory cells provides the second charge in the corresponding body region. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 23, 26)
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17. An integrated circuit comprising:
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semiconductor memory cell comprising an electrically floating body transistor, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the electrically floating body transistor comprising; a first region having impurities to provide a first conductivity type; a second region having impurities to provide the first conductivity type, a body region disposed between the first region, the second region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; a gate spaced apart from the body region and separated therefrom by a gate dielectric; and wherein the memory cell includes; a first data state representative of a first charge in the body region of the transistor; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing carriers from the body region through the gate; and control circuitry, coupled to the memory cell, to generate control signals, including first control signals, to program one of a plurality of data states into the memory cell, wherein, in response to the first control signals applied to the memory cell, the electrically floating body transistor provides the second charge in the body region of the electrically floating body transistor by removing carriers from the body region through the gate. - View Dependent Claims (18, 19, 20, 21, 24)
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Specification