Structures and methods for heterogeneous low power programmable logic device
First Claim
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1. An integrated circuit, comprising:
- a first partition comprising a plurality of first configurable logic blocks, wherein the first configurable logic blocks are optimized for low power consumption;
a second partition comprising a plurality of second configurable logic blocks, wherein the second configurable logic blocks are optimized for high performance;
a first power rail to provide a low supply voltage to the first configurable logic blocks of the first partition; and
a second power rail to provide a high supply voltage, the high supply voltage greater than the low supply voltage, to the second configurable logic blocks of the second partition.
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Abstract
A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD'"'"'s programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.
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17 Claims
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1. An integrated circuit, comprising:
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a first partition comprising a plurality of first configurable logic blocks, wherein the first configurable logic blocks are optimized for low power consumption; a second partition comprising a plurality of second configurable logic blocks, wherein the second configurable logic blocks are optimized for high performance; a first power rail to provide a low supply voltage to the first configurable logic blocks of the first partition; and a second power rail to provide a high supply voltage, the high supply voltage greater than the low supply voltage, to the second configurable logic blocks of the second partition. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit, comprising:
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a first power rail for providing a low supply voltage; a second power rail for providing a high supply voltage, the high supply voltage greater than the low supply voltage; a plurality of partitions, each comprising; a number of configurable logic blocks, each having a power terminal; and means for selectively connecting the configurable logic blocks in the partition to one of the first power rail and the second power rail; and a plurality of programmable level-shifter circuits, each positioned between a corresponding pair of configurable logic blocks and configured to selectively level-shift signals transmitted between the corresponding pair of configurable logic blocks in response to a corresponding level-shifting control signal. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification