Power amplifier with bias control

• US 7,477,106 B2
• Filed: 11/20/2003
• Issued: 01/13/2009
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: Ampleon Netherlands B.V. (Ampleon Coöperatief UA)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van Bezooijen, Adrianus, Prikhodko, Dmitry Pavlovich
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Flanagan, Krista M
• Application Number:
  US10/539,383
• Publication Number:
  US 20060145766A1
• Time in Patent Office: 1,881 Days
• Field of Search: None
• US Class Current: 330/296
• CPC Class Codes: H03F 1/30 Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in differential amplifiers H03F3/45479
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages

Abstract

A power amplifier (100) suitable for use in mobile telecommunications equipment has a first stage (2) and an optional second stage (2), each stage being provided with a bias circuit (4, 5). To provide a well-defined gain characteristic, in the first stage (1) a bias current (Ib1) is fed into a signal amplifying transistor (T1). The first bias circuit (4) comprises non-linear a voltage/current converter (41) coupled to a current mirror (40). To suit alternative applications, such as GSM and UMTS requiring a different bias, plural voltage/current converters (41, 42) may be provided in parallel.

Claims

1. A power amplifier comprising:

a first stage including a signal amplification transistor for amplifying an input signal, the signal amplification transistor having a control electrode responsive to a bias current, and

a first bias circuit including a controlled current source for converting a gain control voltage to the bias current, wherein the bias circuit includes a non-linear voltage/current converter for converting the gain control voltage to the bias current.

2. The power amplifier according to claim 1, wherein the non-linear voltage/current converter coupled to a current mirror for providing the bias current to the control electrode.

3. The power amplifier according to claim 2, wherein the non-linear voltage/current converter includes at least one differential stage coupled to a reference voltage.

5. The power amplifier according to claim 1, wherein the first bias circuit further includes bias voltage means for providing a bias voltage to the first stage.

7. The power amplifier according claim 1, further comprising:

a second stage for amplifying a signal output by the first stage;

a second bias circuit for providing a second stage bias current to the second stage;

a third stage for amplifying a signal output by the second stage; and

third bias circuit for providing a third stage bias current to the third stage.

8. The power amplifier according to claim 1, wherein the power amplifier is arranged for amplifying high frequency signals.

9. A device provided with a power amplifier according to claim 1.

4. A power amplifier comprising:

a first stage for amplifying an input signal, and

a first bias circuit for providing a bias current to the first stage,

the first bias circuit including a controlled current source, and the first bias circuit being arranged for feeding its bias current to a control electrode of a signal amplification transistor of the first stage, wherein at least one bias circuit comprises two distinct voltage/current converters for converting two distinct gain control voltages.

6. A power amplifier comprising:

a first stage for amplifying an input signal, and

a first bias circuit for providing a bias current to the first stage,

the first bias circuit including a controlled current source and a voltage/current converter, and the first bias circuit being arranged for feeding its bias current to a control electrode of a signal amplification transistor of the first stage, wherein in the first bias circuit an additional transistor is coupled between the voltage/current converter and the controlled current source so as to compensate for a DC current gain of the signal amplification transistor.