Shift register
First Claim
Patent Images
1. A shift register having a plurality of stages, each stage comprising:
- first, second, and third driving voltage supply lines;
at least two clock signal supply lines;
an output buffer having an output pull-up transistor and first arid second output pull-down transistors;
a first controller having an input connected to a start signal supply line and an output connected to a first node; and
a second controller having an input connected to the first and second voltage supply lines and an output connected to gates of the first and second output pull-down transistors,wherein high voltages are alternately applied to gates of the first and second output pull-down transistors every predetermined frame;
wherein the first and second output pull-down transistors are connected to second and third nodes, respectively; and
wherein first and second driving voltages supplied to the first and second voltage supply lines have voltages alternately inverted with respect to each other every predetermined frame.
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Abstract
Disclosed is a shift register capable of mitigating gate bias stress. The shift register, including a plurality of stages, includes an output buffer having a pull-up transistor and two pull-down transistors, each with gates connected to different nodes. One of the two pull-down transistors operates during an even frame portion of an LCD operation; and the other of the two pull-down transistors operates during an odd frame portion of the LCD display operation. Alternating operation of the pull-down transistors substantially mitigates gate stress, and substantially enables the shift register to be fabricated with amorphous silicon.
31 Citations
18 Claims
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1. A shift register having a plurality of stages, each stage comprising:
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first, second, and third driving voltage supply lines; at least two clock signal supply lines; an output buffer having an output pull-up transistor and first arid second output pull-down transistors; a first controller having an input connected to a start signal supply line and an output connected to a first node; and a second controller having an input connected to the first and second voltage supply lines and an output connected to gates of the first and second output pull-down transistors, wherein high voltages are alternately applied to gates of the first and second output pull-down transistors every predetermined frame; wherein the first and second output pull-down transistors are connected to second and third nodes, respectively; and wherein first and second driving voltages supplied to the first and second voltage supply lines have voltages alternately inverted with respect to each other every predetermined frame. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A shift register having a plurality of stages, each stage comprising:
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an output buffer having a first transistor and second and third transistors, the second and third transistors having the same polarity; a first controller for controlling an output state of the output buffer; and a second controller for switching an output control between the second and third transistors, wherein high voltages are alternately applied to gates of the second and third transistors every predetermined frame; wherein the second and third transistors are connected to second and third nodes, respectively; and wherein first and second driving voltages supplied to first and second voltage supply lines have voltages alternately inverted with respect to each other every predetermined frame. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification